| Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
| IE, SIP, ICD, IPSJ-SLDM |
2004-10-22
13:25 |
Yamagata |
|
IEEE802.11a Based Wireless A/V Data Transmission System
Takashi Wakutsu, Naohisa Shibuya, Eiji Kamagata, Takaaki Matsumoto, Yasushi Nagahori, Takafumi Sakamoto, Yasuo Unekawa, Kiyohito Tagami, Mutsumu Serizawa (Toshiba) |
The MPEG Audio/Video Standard Definition (SD) data transmission system using IEEE802.11a LAN is developed.
This system ... [more] |
SIP2004-96 ICD2004-128 IE2004-72
pp.43-48 |
| IE, SIP, ICD, IPSJ-SLDM |
2004-10-22
13:50 |
Yamagata |
|
Implementation of IEEE802.11i Cipher Algorithms for Embedded Systems
Motoki Kimura, Yukio Mitsuyama, Takao Onoye (Osaka Univ.), Isao Shirakawa (Hyogo Univ.) |
[more] |
SIP2004-97 ICD2004-129 IE2004-73
pp.49-54 |
| IE, SIP, ICD, IPSJ-SLDM |
2004-10-22
14:15 |
Yamagata |
|
A class-D amplifier using a spectrum shaping technique
Akira Yasuda (Hosei Univ.), Takashi Kimura, Koichiro Ochiai, Toshihiko Hamasaki (TI Japan) |
In this paper, we propose a new class-D amplifier with a lower-frequency reference signal by using a spectrum shap-ing t... [more] |
SIP2004-98 ICD2004-130 IE2004-74
pp.55-60 |
| IE, SIP, ICD, IPSJ-SLDM |
2004-10-22
15:00 |
Yamagata |
|
Improvement of Free Viewpoint VoD System by Introducing Curved Dynamic Background Buffering
Akio Ishikawa, Atsushi Matsumura, Ryoichi Kawada, Atsushi Koike (KDDI Labs.) |
It is important problem that the quality of the output images can be degraded because of lack of information on occluded... [more] |
SIP2004-99 ICD2004-131 IE2004-75
pp.61-66 |
| IE, SIP, ICD, IPSJ-SLDM |
2004-10-22
15:25 |
Yamagata |
|
A Global Routing Problem Generation Method based on Rent's Rule
Kazuhide Takatsuji, Yoichi Shiraishi (Gunma Univ.) |
This paper presents a method which generates global routing problems based on Rent's Rule. In the layout synthesis of ... [more] |
SIP2004-100 ICD2004-132 IE2004-76
pp.67-72 |
| IE, SIP, ICD, IPSJ-SLDM |
2004-10-22
15:50 |
Yamagata |
|
Bus architecture optimization method for IP-based design
Kyoko Ueda, Keishi Sakanushi, Noboru Yoneoka, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.) |
In IP-based design, to find the optimal bus architecture is very important problem because bus architecture strongly aff... [more] |
SIP2004-101 ICD2004-133 IE2004-77
pp.73-78 |
| IE, SIP, ICD, IPSJ-SLDM |
2004-10-22
16:15 |
Yamagata |
|
Design of Cell Assignment Circuit for Dynamic Reconstruction
Yutaka Koseki, Akinori Kanasugi (Tokyo Denki Univ.) |
[more] |
SIP2004-102 ICD2004-134 IE2004-78
pp.79-84 |
| CPSY, VLD, IPSJ-SLDM |
2005-01-25
09:30 |
Kanagawa |
|
A Reconfigurable Processor based on ALU array architecture with limitation on the interconnection
Makoto Okada, Tatsuo Hiramatsu, Hiroshi Nakajima, Makoto Ozone, Katsunori Hirase (SANYO Electric), Shinji Kimura (Waseda Univ.) |
Dynamic reconfigurable processor based on ALU array architecture for consumer appliances is introduced. We propose the A... [more] |
VLD2004-97 CPSY2004-63
pp.1-6 |
| CPSY, VLD, IPSJ-SLDM |
2005-01-25
10:00 |
Kanagawa |
|
Reconfigurable 1-bit processor array with reduced wiring area
Nobuo Nakai, Masaki Nakanishi, Shigeru Yamashita, Katsumasa Watanabe (NAIST) |
Semiconductor makers have a problem of how to reduce the production cost. Because of the increasing gates to implement a... [more] |
VLD2004-98 CPSY2004-64
pp.7-12 |
| CPSY, VLD, IPSJ-SLDM |
2005-01-25
10:30 |
Kanagawa |
|
A variable clock mechanism for Dynamically Reconfigurable Processors
Hideharu Amano, Yoshinori Adachi, Satoshi Tsutsumi, Kenichiro Ishikawa (Keio Univ.) |
[more] |
VLD2004-99 CPSY2004-65
pp.13-16 |
| CPSY, VLD, IPSJ-SLDM |
2005-01-25
11:00 |
Kanagawa |
|
An asynchronous multi-context device with new context switching method
Yoshinori Adachi, Satoshi Tsutsumi, Hideharu Amano (Keio Univ.) |
[more] |
VLD2004-100 CPSY2004-66
pp.17-22 |
| CPSY, VLD, IPSJ-SLDM |
2005-01-25
11:30 |
Kanagawa |
|
A Discussion on Fault Tolerance of Dynamic Reconfigurable Device
Naoki Ochi, Kentaro Nakahara, Futoshi Morie, Shin'ichi Kouyama, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura (Kyoto Univ.) |
Reconfigurable logic devices are expected to be key devices for systems in severe environment such as spacecrafts, satel... [more] |
VLD2004-101 CPSY2004-67
pp.23-28 |
| CPSY, VLD, IPSJ-SLDM |
2005-01-25
13:00 |
Kanagawa |
|
[Invited Talk]
Basics and Goals of Assertion-Based Verification
Kiyoharu Hamaguchi (Osaka Univ.) |
[more] |
VLD2004-102 CPSY2004-68
pp.29-34 |
| CPSY, VLD, IPSJ-SLDM |
2005-01-25
13:30 |
Kanagawa |
|
[Invited Talk]
*
Masanori Imai (STARC) |
Growing complexity of SoC’s and reducing life cycle time of electronic products both are demanding higher design product... [more] |
VLD2004-103 CPSY2004-69
pp.35-38 |
| CPSY, VLD, IPSJ-SLDM |
2005-01-25
14:10 |
Kanagawa |
|
A dividing technique of assertions for an interface protocol used in a divide and conquer approach of formal verification
Hironao Matsushima, Akira Kitajima (OECU) |
[more] |
VLD2004-104 CPSY2004-70
pp.39-44 |
| CPSY, VLD, IPSJ-SLDM |
2005-01-25
14:40 |
Kanagawa |
|
Crosstalk Driven Placement Procedure
Masakazu Ochiai, Masaya Yoshikawa, Takeshi Fujino, Hidekazu Terai (Ritsumeikan University) |
This paper presents a crosstalk reduction method. At the stage of the placement processing, we considered that the effec... [more] |
VLD2004-105 CPSY2004-71
pp.45-50 |
| CPSY, VLD, IPSJ-SLDM |
2005-01-25
15:20 |
Kanagawa |
|
An Instance-Specific Hardware Algorithm Using FPGAs for the Mimimum Vertex Cover Problem of a Graph
Kenji Kikuchi, Shin'ichi Wakabayashi (Hiroshima City Univ.) |
This report presents a hardware algorithm for finding a minimum vertex cover of a given graph, and shows experimental ev... [more] |
VLD2004-106 CPSY2004-72
pp.51-56 |
| CPSY, VLD, IPSJ-SLDM |
2005-01-25
15:50 |
Kanagawa |
|
Solving SAT problem by PCMGTP on FPGA
Shohei Kinoshita, Junichi Matsuda, Hiroshi Fujita, Miyuki Koshimura, Ryuzo Hasegawa (Kyushu Univ) |
In this paper, a new design of the SAT solver PCMGTP implemented on an FPGA chip is described. Although the previous imp... [more] |
VLD2004-107 CPSY2004-73
pp.57-62 |
| CPSY, VLD, IPSJ-SLDM |
2005-01-25
16:20 |
Kanagawa |
|
Design of cellular simulation platform for SBML model
Yow Iwaoka, Yasunori Osana, Tomonori Fukushima, Masato Yoshimi (Keio Univ.), Akira Funahashi, Noriko Hiroi (JST), Yuichiro Shibata, Naoki Iwanaga (Nagasaki Univ.), Hiroaki Kitano (JST), Hideharu Amano (Keio Univ.) |
Computer simulation in widely used in biochemistry research.
However, simulating large-scale model requires a large com... [more] |
VLD2004-108 CPSY2004-74
pp.63-68 |
| CPSY, VLD, IPSJ-SLDM |
2005-01-25
16:50 |
Kanagawa |
|
Architecture for Crossover based on Sequence Pair
Ryousuke Kanemitsu, Akinori Bito, Masaya Yoshikawa, Hidekazu Terai (Ritsumeikan University) |
The floor planning technique that uses GA based on the sequence pair for the solution search is proposed and it obtains ... [more] |
VLD2004-109 CPSY2004-75
pp.69-74 |
|