| Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
| ICD |
2005-04-14
09:00 |
Fukuoka |
|
A Read-Static-Noise-Margin-Free SRAM cell for low-Vdd and High-speed applications
Koichi Takeda, Yasuhiko Hagihara (NEC), Yoshiharu Aimoto (NECEL), Masahiro Nomura, Yoetsu Nakazawa (NEC), Toshio Ishii, Hiroyuki Kobatake (NECEL) |
A read-static-noise-margin-free SRAM cell consists of seven transistors, several of which are low-Vt NMOS transistors us... [more] |
ICD2005-1
pp.1-6 |
| ICD |
2005-04-14
09:30 |
Fukuoka |
|
Low-Power Embedded SRAM Modules with Expanded Margins for Writing
Masanao Yamaoka (Hitachi, Ltd.), Noriaki Maeda (Renesas), Yoshihiro Shinozaki (Hitachi ULSI), Yasuhisa Shimazaki, Koji Nii, Shigeru Shimada, Kazumasa Yanagisawa (Renesas), Takayuki Kawahara (Hitachi, Ltd.) |
The power consumption of a low-power SoC has a battery life of mobile appliances. The general SoCs have large on-chip SR... [more] |
ICD2005-2
pp.7-12 |
| ICD |
2005-04-14
10:00 |
Fukuoka |
|
A 256Mb Synchronous Burst DDR SRAM using Single-crystal Silicon Thin Film Transisitor (SSTFT) SRAM cell
Youngho Suh, Hyouyoun Nam, Youngdae Lee, Hungiun An, Sangbeom Kang, Byunggil Choi, Hoon Lim, Choongkeun Kwak, Hyunguen Byun (Samsung) |
[more] |
ICD2005-3
pp.13-17 |
| ICD |
2005-04-14
10:40 |
Fukuoka |
|
[Invited Talk]
DRAM in the Nanoscale Era
-- Non-1T1C approaches --
Tomoyuki Ishii (Hitachi) |
Challenges for future DRAM technology in the nano-scale process generation are introduced. From operational stability p... [more] |
ICD2005-4
pp.19-22 |
| ICD |
2005-04-14
11:40 |
Fukuoka |
|
A 128Mb DRAM Using a 1T Gain Cell(FBC) on SOI
Takashi Ohsawa, Katsuyuki Fujita, Kosuke Hatsuda (Toshiba), Tomoki Higashi (Toshiba Microelectronics), Mutsuo Morikado, Yoshihiro Minami, Tomoaki Shino, Hiroomi Nakajima, Kazumi Inoh, Takeshi Hamamoto, Shigeyoshi Watanabe (Toshiba) |
We report on a 128Mbit DRAM design using the capacitor-less DRAM cell or the floating body cell(FBC) on SOI. The cell of... [more] |
ICD2005-5
pp.23-28 |
| ICD |
2005-04-14
13:00 |
Fukuoka |
|
[Invited Talk]
*
Hiroyuki Yamauchi (Matsushita) |
Based on the actual examples of where, how and why each memory is used, the representative embedded memories are classif... [more] |
ICD2005-6
pp.29-34 |
| ICD |
2005-04-14
14:00 |
Fukuoka |
|
A 196-mm2, 2-Gb DDR2 SDRAM using an 80-nm Triple Metal Technology
Jeong Hoon kook, Kyehyun Kyung, Chiwook Kim, Jaeyoung Lee (Samsung) |
[more] |
ICD2005-7
pp.35-36 |
| ICD |
2005-04-14
14:30 |
Fukuoka |
|
[Invited Talk]
Statistical Integration In Multigigabit DRAM Design
Tomonori Sekiguchi, Satoru Akiyama (Hitachi), Kazuhiko Kajigaya (Elpida), Satoru Hanzawa, Riichiro Takemura, Takayuki Kawahara (Hitachi) |
Concordant memory-array design incorporates device fluctuations statistically into signal-to-noise ratio analysis in DRA... [more] |
ICD2005-8
pp.37-42 |
| ICD |
2005-04-14
15:15 |
Fukuoka |
|
Improved write methods for 64Mb Phase-change Random Access Memory (PRAM)
Hyung-rok Oh, Beak-hyung Cho, Woo Yeong Cho, Sangbeom Kang, Byung-gil Choi, Hye-jin Kim, Ki-sung Kim, Du-eung Kim, Choong-keun Kwak, Hyun-geun Byun, Gi-tae Jeong, Hong-sik Jeong, Kinam Kim (Samsung) |
[more] |
ICD2005-9
pp.43-45 |
| ICD |
2005-04-14
15:45 |
Fukuoka |
|
A 146mm2 8Gb NAND Flash Memory with 70nm CMOS Technology
Takumi Abe, Takahiko Hara, Koichi Fukuda, Kazuhisa Kanazawa, Noboru Shibata, Koji Hosono, Hiroshi Maejima, Michio Nakagawa, Masatsugu Kojima, Masaki Fujiu, Yoshiaki Takeuchi, Kazumi Amemiya, Midori Morooka (Toshiba), Teruhiko Kamei, Hiroaki Nasu (SanDisk) |
[more] |
ICD2005-10
pp.47-52 |
| ICD |
2005-04-14
16:15 |
Fukuoka |
|
4Gb Multilevel AG-AND Flash Memory with 10MB/s Programming Throughput
Hideaki Kurata, Yoshitaka Sasago, Kazuo Otsuga, Tsuyoshi Arigane, Tetsufumi Kawamura, Takashi Kobayashi, Hitoshi Kume (Hitachi), Kazuki Homma, Kenji Kozakai, Satoshi Noda, Teruhiko Ito, Masahiro Shimizu, Yoshihiro Ikeda, Osamu Tsuchiya, Kazunori Furusawa (RENESAS) |
We fabricated a 4Gb multilevel AG-AND flash memory using 90nm CMOS technology. By using an inversion-layer local-bitline... [more] |
ICD2005-11
pp.53-58 |
| ICD |
2005-04-14
19:00 |
Fukuoka |
|
*
Katsuyuki Sato (Elpida), Hiroyuki Yamauchi (Matsushita), Kenji Numata (Toshiba), Takashi Akazawa (Renesas), Yasunao Katayama (IBM Japan) |
[more] |
ICD2005-12
p.59 |
| ICD |
2005-04-15
10:30 |
Fukuoka |
|
A 1.2V 1Mbit Embedded MRAM Core with Folded Bit-Line Array Architecture
Takaharu Tsuji (Renesas Technorogy), Hiroaki Tanizaki (Renesas Device Design), Masatoshi Ishikawa, Jun Otani, Yuichiro Yamaguchi, Shuichi Ueno, Tsukasa Oishi, Hideto Hidaka (Renesas Technorogy) |
A 1Mbit MRAM with a 0.81um2 1-Transistor 1-Magnetic Tunnel Junction (1T-1MTJ) cell using 0.13um 4LM logic technology has... [more] |
ICD2005-13
pp.1-6 |
| ICD |
2005-04-15
11:00 |
Fukuoka |
|
High Density and Low Power Nonvolatile FeRAM Memory Cell Architecture
Takashi Miki, Hiroshige Hirano, Masahiko Sakagami, Tetsuji Nakakuma, Kunisato Yamaoka, Shunichi Iwanari, Yasuo Murakuki, Yasushi Gohou, Eiji Fujii (Matsushita Electric Industrial Co., Ltd.) |
[more] |
ICD2005-14
pp.7-12 |
| ICD |
2005-04-15
11:30 |
Fukuoka |
|
Burst-Cycle Data Compression Schemes for Pre-Fuse Wafer-Level Test in Large Scale High-Speed embedded DRAM
Ryo Fukuda, Kenji Kobayashi (Toshiba Corp.), Masashi Akamatsu, Minoru Kaihatsu, Atsushi Tamura, Kazuo Taniguchi (Sony Corp.), Yohji Watanabe (Toshiba Corp.) |
This paper describes two novel data compression schemes suitable for high density and high speed embedded DRAMs. The par... [more] |
ICD2005-15
pp.13-17 |
| ICD |
2005-04-15
13:00 |
Fukuoka |
|
A 1.5-ns Access-Time 0.25-μm CMOS/SIMOX SRAM Macrocell
-- High Speed and Low-Power Operation by Using Dual-Wordline Scheme --
Nobutaro Shibata, Takako Ishihara (NTT), Shigehiro Kurita, Hideomi Okiyama (NEL) |
This paper presents high speed and low-power circuit techniques for small size SRAMs (e.g., on-chip cache memories). Rea... [more] |
ICD2005-16
pp.19-24 |
| ICD |
2005-04-15
13:30 |
Fukuoka |
|
Application of Bank-Based Multiport Memory to the Microprocessor Caches
Koh Johguchi, Zhaomin Zhu (Hiroshima Univ.), Tai Hirakawa (Hiroshima City Univ.), Hans Juergen Mattausch, Tetsushi Koide (Hiroshima Univ.), Tetsuo Hironaka, Kazuya Tanigawa (Hiroshima City Univ.) |
[more] |
ICD2005-17
pp.25-30 |
| ICD |
2005-04-15
14:00 |
Fukuoka |
|
Analysys of SRAM neutron-Induced Errors Based on the Consideration of Both Charge-Collection and Parasitic-BipolarFailure Modes
Kenichi Osada (Hitachi), Naoki Kitai (Hitachi ULSI), Shiro Kamohara (Renesas), Takayuki Kawahara (Hitachi) |
This paper describes an investigation of the upsetting of values in cells hit by alpha particles or neutrons, in which t... [more] |
ICD2005-18
pp.31-36 |
| ICD |
2005-04-15
14:30 |
Fukuoka |
|
New Development of Neutron-induced Soft-Error Simulation Technology
Taiki Uemura, Yoshiharu Tosaka, Yoshio Ashizawa, Hideki Oka, Shigeo Satoh (Fujitsu lab.) |
In these years, the interest in soft error becomes increasing. This comes from the problem that the soft error occurs no... [more] |
ICD2005-19
pp.37-42 |
| ICD |
2005-05-26
10:00 |
Hyogo |
Kobe Univ. |
A Low-power Systolic Array Architecture for Block-matching Motion Estimation
Junichi Miyakoshi, Yuichiro Murachi (Kobe Univ.), Koji Hamano, Tetsuro Matsuno, Masayuki Miyama, Masahiko Yoshimoto (Kanazawa Univ.) |
(Advance abstract in Japanese is available) [more] |
ICD2005-20
pp.1-6 |
| ICD |
2005-05-26
10:30 |
Hyogo |
Kobe Univ. |
A Single-Chip Multi-Processor integrating Quadruple Processors on 90nm CMOS Process
Ken-ichi Kawasaki, Tetsuyoshi Shiota, Yukihito Kawabe, Wataru Shibamoto, Atsushi Sato, Tetsutaro Hashimoto, Motoaki Matsumura, Hiroshi Okano, Fumihiko Hayakawa, Shinichiro Tago, Yasuki Nakamura (Fujitsu Labs.), Hideo Miyake (FLT), Atsuhiro Suga, Hiromasa Takahashi, Atsuki Inoue (Fujitsu Labs.) |
We have developed a 51.2-GOPS single-chip multi-processor integrating quadruple processors with 1.0-GB/s system-bus dire... [more] |
ICD2005-21
pp.7-12 |
| ICD |
2005-05-26
11:00 |
Hyogo |
Kobe Univ. |
An H.264/MPEG-4 Audio/Visual Codec LSI with Module-Wise Dynamic Voltage/Frequency Scaling
Yoshiyuki Kitasho, Toshihide Fujiyoshi, Shinichiro Shiratake, Tsuyoshi Nishikawa, Mototsugu Hamada, Hiroyuki Hara, Tetsuya Fujita, Fumitoshi Hatori, Takayoshi Shimazawa, Masami Murakata, Fumihiro Minami, Naoyuki Kawabe, Takeshi Kitahara, Masafumi Takahashi, Yukihito Oowaki (TOSHIBA) |
A single-chip MPEG-4 audiovisual LSI with ability of CIF 15fps encoding is fabricated in a 0.13um CMOS, 5-layer metal te... [more] |
ICD2005-22
pp.13-18 |
| ICD |
2005-05-26
11:30 |
Hyogo |
Kobe Univ. |
A Sheet-Type Scanner Based on a 3D Stacked Organic-Transistor Circuit with Double Word-line and Double Bit-line Structure
Hiroshi Kawaguchi, Shingo Iba, Yusaku Kato, Tsuyoshi Sekitani, Takao Someya, Takayasu Sakurai (Univ. of Tokyo) |
Double word-line and bit-line structure in an organic FET-based sheet-type scanner is described. This structure reduces ... [more] |
ICD2005-23
pp.19-21 |
| ICD |
2005-05-26
13:00 |
Hyogo |
Kobe Univ. |
A Loop-Bandwidth Calibration System for Fractional-N Synthesizer and ΔΣ PLL Transmitter
Yukinori Akamine, Manabu Kawabe, Kazuyuki Hori, Takao Okazaki (Hitachi), Nigel Tolson (RTE), Masumi Kasahara (Renesas), Satoshi Tanaka (Hitachi) |
In this presentation, we propose a new calibration method for loop gain of a delta-sigma PLL transmitter, that can tune ... [more] |
ICD2005-24
pp.23-28 |
| ICD |
2005-05-26
13:30 |
Hyogo |
Kobe Univ. |
A 1.2V 3.5mW Delta-Sigma Modulator with a Passive Current Summing Network and a Variable Gain Function
Toshiaki Nagai, Hiroyuki Satou, Hiroshi Yamazaki, Yuu Watanabe (Fujitsu Ltd.) |
(Advance abstract in Japanese is available) [more] |
ICD2005-25
pp.29-33 |
| ICD |
2005-05-26
14:00 |
Hyogo |
Kobe Univ. |
A CMOS Rotary Encoder System Based on Magnetic Pattern Analysis with a Resolution of 10b per Rotation
Kazuhiro Nakano (Shizuoka Univ.), Toru Takahashi, Yoshitaka Nagano (NTN), Shoji Kawahito (Shizuoka Univ.) |
This paper presents a single-chip CMOS magnetic rotary encoder system based on magnetic pattern analysis. A rotary encod... [more] |
ICD2005-26
pp.35-40 |
| ICD |
2005-05-26
14:30 |
Hyogo |
Kobe Univ. |
A 19.5b Wide Dynamic Range CMOS Image Sensor with 12b Column-Parallel Cyclic A/D Converters
Masaaki Sasaki (Sendai National College of Tech.), Mitsuhito Mase (Shizuoka Univ.), Shoji Kawahito (Research Institute of Elec., Shizuoka Univ.), Yasuo Wakamori (Yamaha) |
A wide dynamic range CMOS image sensor with burst readout multiple exposure is proposed. In this method, maximaly four d... [more] |
ICD2005-27
pp.41-46 |
| ICD |
2005-05-27
10:00 |
Hyogo |
Kobe Univ. |
A 10-Gb/s Burst-Mode CDR IC in 0.13-um CMOS
Masafumi Nogawa, Kazuyoshi Nishimura, Shunji Kimura, Tomoaki Yoshida, Tomoaki Kawamura, Minoru Togashi, Kiyomi Kumozaki, Yusuke Ohtomo (NTT) |
A 10-Gb/s burst-mode CDR IC was fabricated in a 0.13-$\mu$m CMOS process for the high-speed packet-based networks of the... [more] |
ICD2005-28
pp.1-5 |
| ICD |
2005-05-27
10:30 |
Hyogo |
Kobe Univ. |
1.25Gb/s Burst-Mode Receiver ICs with Quick Response for PON systems
Makoto Nakamura, Yuhki Imai, Yohtaro Umeda, Jun Endo, Yuji Akatsu (NTT) |
We have developed 1.25-Gbit/s burst-mode receiver ICs for optical access networks. We devised a quick-response receiver ... [more] |
ICD2005-29
pp.7-11 |
| ICD |
2005-05-27
11:00 |
Hyogo |
Kobe Univ. |
12Gb/s duobinary signaling with x2 oversampled edge equalization
Kouichi Yamaguchi, Kazuhisa Sunaga, Shunichi Kaeriyama, Takaaki Nedachi, Makoto Takamiya, Koichi Nose, Yoshihiro Nakagawa (NEC), Mitsutoshi Sugawara (NEC-EL America), Muneo Fukaishi (NEC) |
A backplane transceiver in 90nm CMOS that employs duobinary signaling over copper traces is described. To introduce duob... [more] |
ICD2005-30
pp.13-18 |
| ICD |
2005-05-27
11:30 |
Hyogo |
Kobe Univ. |
A 950MHz Rectifier Circuit for Sensor Networks with 10m Distance
Toshiyuki Umeda, Hiroshi Yoshida, Shuichi Sekine, Yumi Fujita, Takuji Suzuki, Shoji Otaka (TOSHIBA) |
This paper presents a wireless power transmission system and a high-sensitivity rectifier circuit for ubiquitous sensor ... [more] |
ICD2005-31
pp.19-24 |
| ICD |
2005-05-27
13:00 |
Hyogo |
Kobe Univ. |
A Single-Chip Si-LDMOS Power Amplifier for GSM
Toshihiko Shimizu, Yoshikuni Matsunaga, Satoshi Sakurai (Renesas), Isao Yoshida (ATN), Masao Hotta (Musashi Inst. of Tech.) |
A single-chip Si-LDMOS high-power amplifier with matching circuits and all control blocks for quad-band GSM handset phon... [more] |
ICD2005-32
pp.25-29 |
| ICD |
2005-05-27
13:30 |
Hyogo |
Kobe Univ. |
Integrated stereo sigma-delta class D amplifier
Eric Gaalaas (ADI), Bill Liu, Naoaki Nishimura (ADKK) |
(Advance abstract in Japanese is available) [more] |
ICD2005-33
pp.31-34 |
| ICD |
2005-05-27
14:00 |
Hyogo |
Kobe Univ. |
A 0.18um 102dB-SNR Mixed CT SC Audio-Band delta-sigma ADC
Paul Morrow, Maria Chamarro, Colin Lyden, Pablo Ventura (Analog Devices), Andrew Abo (Telegent Systems), Atsushi Matamura, Mike-D Keane, Richard O'Brien, Niall McGuinness, Paschal Minogue, Martin McGranaghan, Johan Mansson, Ivan Ryan (Analog Devices) |
(Advance abstract in Japanese is available) [more] |
ICD2005-34
pp.35-38 |
| ICD |
2005-05-27
14:30 |
Hyogo |
Kobe Univ. |
Spread-Spectrum Clock Generator for Serial ATA using Fractional PLL controlled by Delta-Sigma Modulator with Level Shifter
Takashi Kawamoto, Masaru Kokubo, Takashi Oshima (Hitachi Ltd), Takayuki Noto, Masato Suzuki, Shigeyuki Suzuki, Takashi Hayasaka, Tomoaki Takahashi, Jun Kasai (Renesas Technology Corp.) |
The spread spectrum clock generator (SSCG) for Serial ATA with a new architecture is fabricated in a 0.15um CMOS process... [more] |
ICD2005-35
pp.39-44 |
| ICD |
2005-05-27
15:10 |
Hyogo |
Kobe Univ. |
A 195Gb/s 1.2W 3D-Stacked Inductive Inter-Chip Wireless Superconnect with Transmit Power Control Scheme
Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue (Keio Univ.), Takayasu Sakurai (Univ. of Tokyo), Tadahiro Kuroda (Keio Univ.) |
A wireless interface by inductive coupling achieves aggregate data rate of 195Gb/s among 4 stacked chips in a package by... [more] |
ICD2005-36
pp.45-50 |
| ICD |
2005-05-27
15:40 |
Hyogo |
Kobe Univ. |
A 3D-Integration Scheme Utilizing Wireless Interconnections for Implementing Hyper Brains
Atsushi Iwata, Mamoru Sasaki, Takamaro Kikkawa, Seiji Kameda, Hiroshi Ando, Kentaro Kimoto, Daisuke Arizono, Hideo Sunami (Hiroshima Univ.) |
(Advance abstract in Japanese is available) [more] |
ICD2005-37
pp.51-56 |
| ICD |
2005-05-27
16:10 |
Hyogo |
Kobe Univ. |
A Programmable On-Chip Picosecond Jitter Measurement Circuit without a Reference Clock
Kiyotaka Ichiyama, Masahiro Ishida, Takahiro Yamaguchi (Advantest Labs.), Mani Soma (Univ. of Washington), Masakatsu Suda, Toshiyuki Okayasu, Daisuke Watanabe, Kazuhiro Yamamoto (Advantest) |
A new on-chip jitter measurement circuit, which does not require a reference clock, is proposed. It consists of a combin... [more] |
ICD2005-38
pp.57-60 |
| ICD |
2005-05-27
16:40 |
Hyogo |
Kobe Univ. |
Substrate Integrity Beyond 1GHz
Mitsuya Fukazawa, Makoto Nagata (Kobe Univ.), Naoyuki Hamanishi, Masazumi Shiochi, Tetsuya Iida (Toshiba Corp.), Junichiro Watanabe (Toshiba Information Systems(Japan) Corp.), Yoshitaka Murasaka, Atsushi Iwata (A-R-Tec Corp.) |
(Advance abstract in Japanese is available) [more] |
ICD2005-39
pp.61-64 |
| ICD |
2005-07-14
09:30 |
Aichi |
Toyohashi Univ. of Tech. |
On-Chip Multi-Channel Waveform Monitoring for Diagnostics of Mixed-Signal VLSI Circuits
Koichiro Noguchi, Makoto Nagata (Kobe Univ.) |
[more] |
ICD2005-40
pp.1-6 |
| ICD |
2005-07-14
09:55 |
Aichi |
Toyohashi Univ. of Tech. |
Evaluation of Digital Crosstalk Noise to CMOS-PLL through Si Substrate
Akihiro Toya, Ayako Kouno, Atsushi Iwata (Hiroshima Univ.), Makoto Nagata (Kobe Univ.), Yoshitaka Murasaka (A-R-Tec) |
[more] |
ICD2005-41
pp.7-12 |
| ICD |
2005-07-14
10:20 |
Aichi |
Toyohashi Univ. of Tech. |
A Wireless Chip Interconnect Using Resonant Coupling Between Spiral Inductors
Daisuke Arizono, Atsushi Iwata, Mamoru Sasaki (Hiroshima Univ.) |
[more] |
ICD2005-42
pp.13-18 |
| ICD |
2005-07-14
10:45 |
Aichi |
Toyohashi Univ. of Tech. |
Current mode pulse width demodulation circuit for line parallel data transfer
Masaki Odahara, Seiji Kameda, Atsushi Iwata (Hiroshima Univ.) |
[more] |
ICD2005-43
pp.19-24 |
| ICD |
2005-07-14
11:10 |
Aichi |
Toyohashi Univ. of Tech. |
Preproduction of LED driver for Visible Light Communications and Evaluation of response performance of visible LED
Shimpei Miyahara, Satoshi Aono, Yoshinori Matsumoto (keio Univ.) |
Visible Light Communications is a new method of wireless communications with modulating light of visible LED (Light Emit... [more] |
ICD2005-44
pp.25-30 |
| ICD |
2005-07-14
11:35 |
Aichi |
Toyohashi Univ. of Tech. |
オンセンサ2次元動物体追跡の処理方式
吉田 崇, Toshiyuki Sugita, Takayuki Hamamoto (東京理科大) |
[more] |
ICD2005-45
pp.31-36 |
| ICD |
2005-07-14
13:00 |
Aichi |
Toyohashi Univ. of Tech. |
[Invited Talk]
*
越智 成之 (SONY) |
Milestone events and episodes of CCD Development and Commercialization are mainly described during the twenty years from... [more] |
ICD2005-46
pp.37-42 |
| ICD |
2005-07-14
13:50 |
Aichi |
Toyohashi Univ. of Tech. |
*
Masaaki Sasaki (SNCT), Mitsuhito Mase, Shoji Kawahito (Shizuoka Univ.), Yoshiaki Tadokoro (Toyohashi Univ. of Tech.) |
[more] |
ICD2005-47
pp.43-48 |
| ICD |
2005-07-14
14:15 |
Aichi |
Toyohashi Univ. of Tech. |
*
(TI Japan), Shigetoshi Sugawa (Tohoku Univ.), (TI Japan), Nana Akahane (Tohoku Univ.), , (TI Japan) |
[more] |
ICD2005-48
pp.49-53 |
| ICD |
2005-07-14
14:40 |
Aichi |
Toyohashi Univ. of Tech. |
低消費電力アプリケーションに向けた低電圧パルス幅変調方式CMOSイメージセンサ
Keiichiro Kagawa (NAIST), Makoto Shouho (Sharp), Masahiro Nunoshita, Jun Ohta (NAIST) |
In this report, we discuss reduction of analog power supply voltage of CMOS image sensors to achieve low power dissipati... [more] |
ICD2005-49
pp.55-60 |
| ICD |
2005-07-14
15:20 |
Aichi |
Toyohashi Univ. of Tech. |
An evalution of 272 gate count ODRGA_VLSI
Takenori Shiki, Minoru Watanabe, Fuminori Kobayashi (K I T) |
[more] |
ICD2005-50
pp.61-65 |
| ICD |
2005-07-14
15:45 |
Aichi |
Toyohashi Univ. of Tech. |
Reconfiguration Speed Improvement of an ODRGA using VCSELs
Mototsugu Miyano, Minoru Watanabe, Fuminori Kobayashi (KIT) |
[more] |
ICD2005-51
pp.67-70 |
| ICD |
2005-07-14
16:10 |
Aichi |
Toyohashi Univ. of Tech. |
Interface Electronics for MEMS Vibratory Sensors
Kazusuke Maenaka, Nobuhiro Sawai, Takayuki Fujita, Yoichiro Takayama (Univ. of Hyogo) |
A MEMS vibratory acceleration sensor,vibratory gyroscope and their interface circuitry are discussed. Vibratory type sen... [more] |
ICD2005-52
pp.71-76 |
| ICD |
2005-07-14
16:35 |
Aichi |
Toyohashi Univ. of Tech. |
A Study of Detection Circuit for Three-Axis Capacitive Acceleration Sensor
Kouiti Kutuwada, Yoshinori Matsumoto (Keio Univ.) |
In this research, detection circuit for 3-axis capacitive acceleration sensor has been developed by using 0.35um CMOS pr... [more] |
ICD2005-53
pp.77-82 |
| ICD |
2005-07-14
17:00 |
Aichi |
Toyohashi Univ. of Tech. |
Multichannel Si Microprobe Array for Neural Recording on Integrated Circuit
Naoki Funagayama, Takeshi Kawano, Hidekuni Takao, Kazuaki Sawada, Makoto Ishida (Toyohashi Univ. of Tech.) |
This paper reports on development of a Si microprobe array chip for multi-site neural recording. The probe array is real... [more] |
ICD2005-54
pp.83-87 |
| ICD |
2005-07-15
09:30 |
Aichi |
Toyohashi Univ. of Tech. |
A 1V Supply Low Noise CMOS Amplifier Using Noise Reduction Techniques of Autozeroing and Chopper Stabilization
Yoshihiro Masui, Takayuki Mashimo, Takeshi Yoshida, Mamoru Sasaki, Atsushi Iwata (Hiroshima Univ) |
A low-noise CMOS amplifier operating at a 1-V supply voltage is developed using the two noise reduction techniques of au... [more] |
ICD2005-55
pp.1-6 |
| ICD |
2005-07-15
09:55 |
Aichi |
Toyohashi Univ. of Tech. |
JFET-CMOS Low Noise Operational Amplifier for Sensor Interface Applications
Yusuke Edo, Hidekuni Takao, Kazuaki Sawada, Makoto Ishida (Toyohashi Univ. of Tech.) |
In this paper,an integration technology of JFET in CMOS circuits is presented. MOSFETs essentially has large 1/f noise a... [more] |
ICD2005-56
pp.7-12 |
| ICD |
2005-07-15
10:20 |
Aichi |
Toyohashi Univ. of Tech. |
Low voltage, low noise ring-VCO for 1chip wireless sensor LSI
Naoya Ishida, Atsushi Iwata, Mamoru Sasaki, Takeshi Yoshida (Hiroshima Univ) |
[more] |
ICD2005-57
pp.13-17 |
| ICD |
2005-07-15
10:45 |
Aichi |
Toyohashi Univ. of Tech. |
An Image Filtering Processor for Face/Object Recognition Using Merged/Mixed Analog-Digital Architecture
Keisuke Korekado, Takashi Morie (Kyushu Insti. of Tech.), Osamu Nomura (Canon), Teppei Nakano (Kyushu Insti. of Tech.), Masakazu Matsugu (Canon), Atsushi Iwata (Hiroshima Univ.) |
This paper proposes an image-filtering processor LSI based on a hybrid approach using pulse-width modulation (PWM) and d... [more] |
ICD2005-58
pp.19-23 |
| ICD |
2005-07-15
11:10 |
Aichi |
Toyohashi Univ. of Tech. |
[Invited Talk]
*
Tadahiro Kuroda (慶大) |
[more] |
|
| ICD |
2005-07-15
13:00 |
Aichi |
Toyohashi Univ. of Tech. |
A study in the effect of CMOS scaling on the analog circuit performance
-- An effect of design rule on CMOS OPamps and pipeline ADCs --
Masaya Miyahara, Takashi Kurashina, Akira Matsuzawa (Titech) |
[more] |
ICD2005-59
pp.25-30 |
| ICD |
2005-07-15
13:25 |
Aichi |
Toyohashi Univ. of Tech. |
A 14bit Digitally Self-Calibrated Pipelined ADC with Adaptive Bias Optimization for Arbitrary Speeds up to 40MS/s
Hirofumi Matsui, Masaya Ueda, Mutsuo Daito, Kunihiko Iizuka (Sharp) |
A 14bit digitally self-calibrated pipelined ADC featuring the adaptive bias optimization is fabricated in a 0.18μm CMOS ... [more] |
ICD2005-60
pp.31-34 |
| ICD |
2005-07-15
13:50 |
Aichi |
Toyohashi Univ. of Tech. |
*
Toshinori Otaka, Yan Lee, Timothy Bales, Paul Smith, Jonathan MacDowell, Scott Smith, Isao Takayanagi (Micron Japan) |
Ramp analog-to-digital converters (ADC) have been widely used for column-parallel ADCs in imagers for several reasons: s... [more] |
ICD2005-61
pp.35-38 |
| ICD |
2005-07-15
14:15 |
Aichi |
Toyohashi Univ. of Tech. |
[Invited Talk]
Silicon Smart Microsensors based on MEMS-CMOS Integration Technologies
Hidekuni Takao, Kazuaki Sawada, Makoto Ishida (Toyohashi Univ. of Tech.) |
MEMS is a batch fabrication technology of integrated micro structures and electron devices using lithography, material d... [more] |
ICD2005-62
pp.39-44 |
| ICD |
2005-07-15
15:20 |
Aichi |
Toyohashi Univ. of Tech. |
*
Satoshi Aoyama, Shoji Kawahito (Shizuoka Univ.), , Masahiro Yamaguchi (Tohoku Univ.) |
(To be available after the conference date) [more] |
ICD2005-63
pp.45-50 |
| ICD |
2005-07-15
15:45 |
Aichi |
Toyohashi Univ. of Tech. |
非冷却赤外線センサにおける基板温度・自己加熱補正機構
本多 浩大, 藤原 郁夫, 飯田 義典, 重中 圭太郎 (東芝) |
We have developed an uncooled(thermal) infrared sensor with the read-out circuit that can calibrate the substrate temper... [more] |
ICD2005-64
pp.51-56 |
| ICD |
2005-07-15
16:10 |
Aichi |
Toyohashi Univ. of Tech. |
*
Masayuki Ikebe (Hokkaido Univ.), , , , , (DNP) |
[more] |
ICD2005-65
pp.57-62 |
| ICD |
2005-07-15
16:35 |
Aichi |
Toyohashi Univ. of Tech. |
Evaluation and Fabrication of Filter-less Fluorescence Detection Sensor
Yuki Maruyama, Kazuaki Sawada, Hidekuni Takao, Makoto Ishida (Toyohashi Univ. of Tech.) |
A novel filter-less fluorescence detection sensor was successfully fabricated using CMOS integrated circuit technology. ... [more] |
ICD2005-66
pp.63-68 |
| ICD, SDM |
2005-08-18
08:30 |
Hokkaido |
HAKODATE KOKUSAI HOTEL |
A 95mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High Resolution Video Application
Yuichiro Murachi (Kobe Univ.), Koji Hamano, Tetsuro Matsuno (Kanazawa Univ.), Junichi Miyakoshi (Kobe Univ.), Masayuki Miyama (Kanazawa Univ.), Masahiko Yoshimoto (Kobe Univ.) |
This paper describes a 95mW MPEG2 MP@HL motion estimation processor core for portable and high resolution video applicat... [more] |
SDM2005-128 ICD2005-67
pp.1-6 |
| ICD, SDM |
2005-08-18
08:55 |
Hokkaido |
HAKODATE KOKUSAI HOTEL |
An Energy Reduction Method for FFT Circuits in Digital Wireless Communications Using Bitwidth Control
Masayuki Tokunaga, Kosuke Tarumi, Hiroto Yasuura (Kyushu Univ.) |
Recently, digital wireless communication systems become very popular to use in portable devices. Low-energy system imple... [more] |
SDM2005-129 ICD2005-68
pp.7-12 |
| ICD, SDM |
2005-08-18
09:20 |
Hokkaido |
HAKODATE KOKUSAI HOTEL |
TIS Locking Circuit for Compensating LSI Performance by Temperature Variation
Goichi Ono, Masayuki Miyazaki, Kazuki Watanabe, Takayuki Kawahara (Hitachi, Ltd.) |
(Advance abstract in Japanese is available) [more] |
SDM2005-130 ICD2005-69
pp.13-18 |
| ICD, SDM |
2005-08-18
09:45 |
Hokkaido |
HAKODATE KOKUSAI HOTEL |
A Digital Detector Design For Measuring Gate-Delay Variation
Ryota Sakamoto, Masanori Muroyama, Kosuke Tarumi, Hiroto Yasuura (Kyushu Univ.) |
(Advance abstract in Japanese is available) [more] |
SDM2005-131 ICD2005-70
pp.19-24 |
| ICD, SDM |
2005-08-18
10:25 |
Hokkaido |
HAKODATE KOKUSAI HOTEL |
[Special Invited Talk]
*
Makoto Yoshimi (SOITEC Asia) |
[more] |
SDM2005-132 ICD2005-71
pp.25-30 |
| ICD, SDM |
2005-08-18
11:10 |
Hokkaido |
HAKODATE KOKUSAI HOTEL |
Experimental Study on the Mobility Superiority in (110)-oriented Ultra-thin Body pMOSFETs
Gen Tsutsui, Masumi Saitoh, Toshiro Hiramoto (Univ. of Tokyo) |
Ultra-thin body (UTB) SOI MOSFET is one of the most promising structures for future VLSIs because of its high short chan... [more] |
SDM2005-133 ICD2005-72
pp.31-36 |
| ICD, SDM |
2005-08-18
11:35 |
Hokkaido |
HAKODATE KOKUSAI HOTEL |
Variable body-factor FD SOI MOSFET for VTCMOS applications
Tetsu Ohtou, Toshiharu Nagumo, , Toshiro Hiramoto (Univ. Tokyo) |
(Advance abstract in Japanese is available) [more] |
SDM2005-134 ICD2005-73
pp.37-42 |
| ICD, SDM |
2005-08-18
13:00 |
Hokkaido |
HAKODATE KOKUSAI HOTEL |
Measurement and evaluation of delay variation due to inductive and capacitive coupling noise
Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye (Osaka Univ.) |
Capacitive coupling has been considered as a source of interconnect delay variation. Because of progressive increase in ... [more] |
SDM2005-135 ICD2005-74
pp.43-48 |
| ICD, SDM |
2005-08-18
13:25 |
Hokkaido |
HAKODATE KOKUSAI HOTEL |
Isolation Strategy against Substrate Coupling in CMOS Mixed-Signal/RF Circuits
Daisuke Kosaka, Makoto Nagata (Kobe Univ.), Yoshitaka Murasaka, Atsushi Iwata (A-R-Tec Corp.) |
A deep n-well guard-ring, DNW-GR, provides effective isolation from substrate-coupled high frequency noises in combinati... [more] |
SDM2005-136 ICD2005-75
pp.49-54 |
| ICD, SDM |
2005-08-18
13:50 |
Hokkaido |
HAKODATE KOKUSAI HOTEL |
A Test Structure to Analyze (Highly-Doped)/(Lightly-Doped)-Drain in LDD-type CMOSFET
Takashi Ohzone (Okayama Pref. Univ.), Toshihiro Matsuda (Toyama Pref. Univ.), Kazuhiko Okada, Takayuki Morishita, Kiyotaka Komoku (Okayama Pref. Univ.), Hideyuki Iwata (Toyama Pref. Univ.) |
A test structure to separately measure sheet resistances of highly-doped-drain (HDD) and lightly- doped-drain (LDD) in L... [more] |
SDM2005-137 ICD2005-76
pp.55-60 |
| ICD, SDM |
2005-08-18
14:30 |
Hokkaido |
HAKODATE KOKUSAI HOTEL |
Delay Modeling and Static Timing Analysis for MTCMOS Circuits
Naoaki Ohkubo, Kimiyoshi Usami (Shibaura Institute of Tech.) |
One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a dela... [more] |
SDM2005-138 ICD2005-77
pp.61-66 |
| ICD, SDM |
2005-08-18
14:55 |
Hokkaido |
HAKODATE KOKUSAI HOTEL |
Monitoring Scheme for Minimizing Power Consumption by Means of Supply and Threshold Voltage Control in Active and Standby Modes
Yoshifumi Ikenaga, Masahiro Nomura, Koichi Takeda, Yoetsu Nakazawa (NEC), Yoshiharu Aimoto (NECEL), Yasuhiko Hagihara (NEC) |
(Advance abstract in Japanese is available) [more] |
SDM2005-139 ICD2005-78
pp.67-72 |
| ICD, SDM |
2005-08-18
15:20 |
Hokkaido |
HAKODATE KOKUSAI HOTEL |
A Low Dynamic Power and Low Leakage Power CMOS Square-Root Circuit
Nobuaki Kobayashi, Tadayoshi Enomoto (Chuo Univ.) |
(Advance abstract in Japanese is available) [more] |
SDM2005-140 ICD2005-79
pp.73-78 |
| ICD, SDM |
2005-08-18
15:45 |
Hokkaido |
HAKODATE KOKUSAI HOTEL |
A Low Leakage SRAM Macro with Replica Cell Biasing Scheme
Osamu Hirabayashi, Yasuhisa Takeyama, Hiroyuki Otake, Keiichi Kushida, Nobuaki Otsuka (Toshiba Corp.) |
(Advance abstract in Japanese is available) [more] |
SDM2005-141 ICD2005-80
pp.79-84 |
| ICD, SDM |
2005-08-18
16:20 |
Hokkaido |
HAKODATE KOKUSAI HOTEL |
SOI; the Trump Card of SOCs in Sub. 50-nm Era
-- Techniques that SOI Conquers Bulk! --
Tadayoshi Enomoto (Chuo Univ.), Takakuni Douseki (NTT), Kazutami Arimoto (Renesas), Jiroh Ida (Oki), Takashi Ipposhi (Renesas), Kazuhiko Miki (Toshiba), Masanao Yamaoka (Hitachi), Makoto Yoshimi (SOITEC) |
(Advance abstract in Japanese is available) [more] |
SDM2005-142 ICD2005-81
pp.85-90 |
| ICD, SDM |
2005-08-19
08:30 |
Hokkaido |
HAKODATE KOKUSAI HOTEL |
A -90dBc@10kHz Phase Noise Fractional-N Frequency Synthesizer with Accurate Loop Bandwidth Control Circuit
Shiro Dosho, Takashi Morie, Koji Okamoto, Yuji Yamada, Kazuaki Sogawa (Matsushita Electric Industrial Co., Ltd) |
This paper describes a -90dBc@10kHz phase noise fractional-N frequency synthesizer of 110M-180MHz output with accurate l... [more] |
SDM2005-143 ICD2005-82
pp.1-6 |
| ICD, SDM |
2005-08-19
08:55 |
Hokkaido |
HAKODATE KOKUSAI HOTEL |
A Low-IF CMOS Single-Chip Bluetooth EDR Transmitter with Digital I/Q Mismatch Trimming Circuit
Hiroki Ishikuro, Daisuke Miyashita, Taro Shimada, Shouhei Kousai, Hiroyuki Kobayashi, Hideaki Majima, Kenichi Agawa, Mototsugu Hamada, Fumitoshi Hatori (Toshiba) |
A single-chip low-IF transmitter for the Bluetooth Enhanced Data Rate (max. 3Mbps) was fabricated in 0.18-um CMOS proces... [more] |
SDM2005-144 ICD2005-83
pp.7-12 |
| ICD, SDM |
2005-08-19
09:20 |
Hokkaido |
HAKODATE KOKUSAI HOTEL |
A 106dB audio digital-to-analog converter employing segment flipping technology combined with cascaded dynamic element matching
Toru Ido, Sonny Ishizuka (TIJ) |
A 106dB stereo audio digital-to-analog converter having high power supply rejection and reduced jitter
sensitivity usin... [more] |
SDM2005-145 ICD2005-84
pp.13-18 |
| ICD, SDM |
2005-08-19
10:00 |
Hokkaido |
HAKODATE KOKUSAI HOTEL |
[Special Invited Talk]
HfSiON
-- its high applicability as the alternative gate dielectric based on the high thermal stability and the remaining issue --
Akira Nishiyama, Masato Koyama, Yuuichi Kamimuta, Masahiro Koike, Ryosuke Iijima, Takeshi Yamaguchi, Masamichi Suzuki, Tsunehiro Ino, Mizuki Ono (Toshiba) |
The decrease in the MOS device size has long been requiring the thinning of its gate dielectrics. In order to suppress t... [more] |
SDM2005-146 ICD2005-85
pp.19-24 |
| ICD, SDM |
2005-08-19
10:45 |
Hokkaido |
HAKODATE KOKUSAI HOTEL |
HfSiON Gate Dielectrics Design for Mixed Signal CMOS
Kenji Kojima, Ryosuke Iijima, Tatsuya Ohguro, Takeshi Watanabe, Mariko Takayanagi, Hisayo S. Momose, Kazunari Ishimaru, Hidemi Ishiuchi (TOSHIBA) |
(Advance abstract in Japanese is available) [more] |
SDM2005-147 ICD2005-86
pp.25-30 |
| ICD, SDM |
2005-08-19
11:10 |
Hokkaido |
HAKODATE KOKUSAI HOTEL |
Improvement of threshold voltage asymmetry by Al compositional mudulation and partially silicided gate electrode for Hf-based high-k CMOSFETs
Masaru Kadoshima, Arito Ogawa, Masashi Takahashi (MIRAI-ASET), Hiroyuki Ota (MIRAI-ASRC, AIST), Nobuyuki Mise, Kunihiko Iwamoto (MIRAI-ASET), Shinji Migita (MIRAI-ASRC, AIST), Hideaki Fujiwara, Hideki Satake, Toshihide Nabatame (MIRAI-ASET), Akira Toriumi (MIRAI-ASRC, AIST, The Univ. of Tokyo) |
Threshold voltage (Vth) tuning by engineering Fermi-level pinning (FLP) on HfAlOx(N) dielectrics is demonstrated for CMO... [more] |
SDM2005-148 ICD2005-87
pp.31-36 |
| ICD, SDM |
2005-08-19
11:35 |
Hokkaido |
HAKODATE KOKUSAI HOTEL |
Gate work-function modulation in SiON/poly-Si gate stacks, and its impact on low power devices
-- Advantage of sub-monolayer Hf at SiON/poly-Si interface --
Jiro Yugami (Renesas), Yasuhiro Shimamoto (Hitachi), Masao Inoue, Masaharu Mizutani, Takashi Hayashi, Katsuya Shiga, Fumiko Fujita, Jyunichi Tuchimoto, Yoshikazu Ohno, Masahiro Yoneda (Renesas) |
Gate work-function (WF) is controlled by incorporating sub-monolayer Hf at SiON/poly-Si interface. This technique provid... [more] |
SDM2005-149 ICD2005-88
pp.37-42 |
| ICD, SDM |
2005-08-19
13:00 |
Hokkaido |
HAKODATE KOKUSAI HOTEL |
A Novel Voltage Sensing 1T/2MTJ Cell with Resistance Ratio for Highly Stable and Scalable MRAM
Masaki Aoki, Hiroshi Iwasa, Yoshihiro Sato (Fujitsu Lab) |
We propose a new scalable MRAM cell that consists of one transistor (1T) and two magnetic tunnel junctions (2MTJ), and c... [more] |
SDM2005-150 ICD2005-89
pp.43-48 |
| ICD, SDM |
2005-08-19
13:25 |
Hokkaido |
HAKODATE KOKUSAI HOTEL |
0.5V Asymmetric Three-Tr. Cell (ATC) DRAM Using 90nm Generic CMOS Logic Process
Motoi Ichihashi, Haruki Toda, Yasuo Itoh, Koichiro Ishibashi (STARC) |
Asymmetric Three-Tr. Cell (ATC) DRAM which has one P- and two N-MOS transistors for one unit cell is proposed with "forc... [more] |
SDM2005-151 ICD2005-90
pp.49-54 |
| ICD, SDM |
2005-08-19
13:50 |
Hokkaido |
HAKODATE KOKUSAI HOTEL |
A 0.4-V High-Speed Long-Retention-Time DRAM Array with 12 F2 Twin Cell
Riichiro Takemura, Kiyoo Itoh, Tomonori Sekiguchi, Satoru Akiyama, Satoru Hanzawa (Hitachi), Kazuhiko Kajigaya (ELPIDA), Takayuki Kawahara (Hitachi) |
We propose and evaluate a DRAM cell array with 12-F2 twin cell in terms of speed, retention time, and low-voltage operat... [more] |
SDM2005-152 ICD2005-91
pp.55-60 |
| ICD, SDM |
2005-08-19
14:15 |
Hokkaido |
HAKODATE KOKUSAI HOTEL |
Selective-Capacitance Constant-Charge-Injection Programming Scheme for High-Speed Multilevel AG-AND Flash Memories
Kazuo Otsuga, Hideaki Kurata (Hitachi, Ltd.), Kenji Kozakai, Satoshi Noda (Renesas), Yoshitaka Sasago, Tsuyoshi Arigane, Tetsufumi Kawamura, Takashi Kobayashi (Hitachi, Ltd.) |
We developed a selective-capacitance constant-charge-injection programming scheme for multilevel AG-AND flash memories. ... [more] |
SDM2005-153 ICD2005-92
pp.61-66 |
| ICD, SDM |
2005-08-19
14:40 |
Hokkaido |
HAKODATE KOKUSAI HOTEL |
Robust Device Design in FinFET SRAM for hp22nm Technology Node
Kimitoshi Okano, Tatsuya Ishida, Takahiko Sasaki, Takashi Izumida, Masaki Kondo, Makoto Fujiwara, Nobutoshi Aoki, Satoshi Inaba, Nobuaki Otsuka, Kazunari Ishimaru, Hidemi Ishiuchi (Toshiba) |
Feasibility of FinFET SRAM operation at hp22nm technology node has been studied by device and circuit simulation from th... [more] |
SDM2005-154 ICD2005-93
pp.67-72 |
| ICD, SDM |
2005-08-19
15:15 |
Hokkaido |
HAKODATE KOKUSAI HOTEL |
High-k; Last Card for the Leakage Currents
Tadayoshi Enomoto (Chuo Univ.), Mariko Takayanagi (Toshiba), Shigeo Satoh (Fujitu), Koji Nii (Renesas), Akira Nishiyama (Toshiba), ハセ タカシ (NEC), Mototsugu Hamada (Toshiba), Jiro Yugami (Renesas) |
(Advance abstract in Japanese is available) [more] |
SDM2005-155 ICD2005-94
pp.73-78 |
| ICD, CPM |
2005-09-08
09:00 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
The comparison of electrical characteristics of FCBGA packaging substrate based on MLTS and conventional build-up PWB
Jun Sakai, Koichiro Nakase (NEC), Hirokazu Honda (NECエレクトロニクス), Hirobumi Inoue (NEC) |
We heve developed an ultra-thin high-density packaging substrate, called an MLTS (multi-layer thin substrate), that cons... [more] |
CPM2005-85 ICD2005-95
pp.1-6 |
| ICD, CPM |
2005-09-08
09:25 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Characteristic dielectric constant for polyimide thin films at 10GHz
Shigemasa Segawa (PI R&D), Sachiko Ito, Katsuya Kikuchi, Kazuhiko Tokoro, Hiroshi Nakagawa, Masahiro Aoyagi (AIST) |
[more] |
CPM2005-86 ICD2005-96
pp.7-12 |
| ICD, CPM |
2005-09-08
09:50 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Development of Design Techniques for Semiconductor-Package By using Simplified DRAM Macro Model of Power System
Satoshi Nakamura, Takashi Suga (Hitachi PERL), Mitsuaki Katagiri, Yoji Nishio, Seiji Funaba, Yukitoshi Hirose, イサ サトシ (Elpida) |
In late years, MCP(Multi Chip Package) and SiP(System in Package) which has plural semiconductor chips in one package be... [more] |
CPM2005-87 ICD2005-97
pp.13-18 |
| ICD, CPM |
2005-09-08
10:30 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Performance evaluation of high-precision manipulator for probing on entire chip surface
Akira Nakada, Keijiro Itakura, Hiroshi Kubota (Kumamoto Univ.) |
[more] |
|
| ICD, CPM |
2005-09-08
10:55 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Visualization of High Frequency Electromagnetic Field over Fine Circuits by Magnetooptic/Electrooptic Probe
Mizuki Iwanami, Shigeki Hoshino, Norio Masuda (NEC), Masato Kishi (Univ. of Tokyo), Masahiro Tsuchiya (NICT) |
To realize a electromagnetic field probe that is capable of contributing to an electrical design, especially a low-noise... [more] |
CPM2005-88 ICD2005-98
pp.19-24 |
| ICD, CPM |
2005-09-08
11:20 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Diagnostic Test Compaction for Combinational and Sequential Circuits
Yoshinobu Higami (Ehime Univ.), Kewal K Saluja (Univ. of Wisconsin), Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu (Ehime Univ.) |
Recently, it is getting important to reduce the cost of test and fault diagnosis.
Since the cost of test and fault diag... [more] |
CPM2005-89 ICD2005-99
pp.25-30 |
| ICD, CPM |
2005-09-08
13:00 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
System Packaging Issue and Solution of Renesas SiP
Noriaki Sakamoto, Norihiko Sugita, Takafumi Kikuchi, Hideki Tanaka, Takashi Akazawa (ルネサステクノロジ) |
[more] |
CPM2005-90 ICD2005-100
pp.31-34 |
| ICD, CPM |
2005-09-08
13:25 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Basic Study of Proper Circuit Line Structure for Advanced System in Package
Shouhei Yasuda (Melco Display Tech.), Yoshiharu Iwata, Ryohei Satoh (Osaka Univ.) |
Although the semiconductor has raised performance by speeding up of the clock frequency and shrinking the process rule, ... [more] |
CPM2005-91 ICD2005-101
pp.35-40 |
| ICD, CPM |
2005-09-08
13:50 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
The Study of Silicon Stress for Stacked Die Packages
Kenji Abe, Eiichi Yamada, Yutaka Suzuki, Masazumi Amagai (TI Japan) |
[more] |
CPM2005-92 ICD2005-102
pp.41-44 |
| ICD, CPM |
2005-09-08
14:30 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
The Study of Stress Sensor for Stacked Die Packages
Yutaka Suzuki, Kenji Abe, Eiichi Yamada, , Masazumi Amagai (TI Japan) |
[more] |
CPM2005-93 ICD2005-103
pp.45-48 |
| ICD, CPM |
2005-09-08
14:55 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Design and fabrication of MOS devices patterning with LCD image projection
Akira Nakada, Satoshi Wakimoto, Hiroshi Kubota (Kumamoto Univ.) |
[more] |
|
| ICD, CPM |
2005-09-08
15:20 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
2 GHz Linear Amplifier Module with Feedforward Linearizer
Hiroyuki Kayano (Toshiba), Yuji Ohtsuka, Masao Suzuki, Masaya Ishiguro (TDMS), Tatsunori Hashimoto (Toshiba) |
A feedforward linearizer amplifier module on a substrate we have developed is described. In particular, we report the ad... [more] |
CPM2005-94 ICD2005-104
pp.49-52 |
| ICD, CPM |
2005-09-08
15:45 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
A CMOS Impulse Radio Ultra-Wideband Transceiver for 1Mb/s Data Communications and ±2.5cm Range Findings
Takahide Terada, Shingo Yoshizumi, Muhammad Muqsith, Yukitoshi Sanada, Tadahiro Kuroda (Keio Univ.) |
[more] |
CPM2005-95 ICD2005-105
pp.53-58 |
| ICD, CPM |
2005-09-09
09:00 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
[Invited Talk]
The study of the high frequency electrical characteristics in high-speed digital device mounting
Chihiro Ueda (AETJAPAN) |
[more] |
CPM2005-96 ICD2005-106
pp.1-5 |
| ICD, CPM |
2005-09-09
09:50 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Analysis of Transmission Characteristic of High-speed Differential Sgnal Bus
Tsuyoshi Tokiwa, Toshio Sudo (Toshiba), Nobuhiro Tsuruta (Toshiba DME), Yoshihiro Nishida (Toshiba DM) |
With performance improvement of CPU, improvement of signal transmission ability between LSI became indispensable. And th... [more] |
CPM2005-97 ICD2005-107
pp.7-12 |
| ICD, CPM |
2005-09-09
10:15 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Measuemnt and Discussion of Degradation of Pulse Feature according with Line Length Increase
Koichi Yabuuchi (EMtech), Tamotsu Usami, Yutaka Akiyama, Kanji Otsuka (Meisei Univ.) |
In this research, the single pulse (1kHz, 100kHz, 10MHz, 100MHz, and 500MHz) was inputted into coaxial cables 1m, 10m, a... [more] |
CPM2005-98 ICD2005-108
pp.13-16 |
| ICD, CPM |
2005-09-09
10:55 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Lead-free bumping and its process integrity for fine pitch interconnects
Hirokazu Ezawa, Masaharu Seto, Kazuhito Higuchi (Toshiba) |
Electroplated solder bumps allow much finer pitch interconnection for high I/O applications, although controlling the al... [more] |
CPM2005-99 ICD2005-109
pp.17-22 |
| ICD, CPM |
2005-09-09
11:20 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Development of New Surface Finish Technology for Package Substrates with Excellent Bondability
Kiyotaka Tsukada (IBIDEN) |
This Paper describes the characteristics, development, and application of
the surface finish technologies for chip pack... [more] |
CPM2005-100 ICD2005-110
pp.23-27 |
| ICD, CPM |
2005-09-09
13:00 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Simultaneous switching noise(SSN) and EMI of a semiconductor package
Takanobu Kushihira (MSC), Toshio Sudo (TSB) |
We tested a series about a Simultaneous Switching Noise(SSN) by influence of the parasitism inductance that a package ha... [more] |
CPM2005-101 ICD2005-111
pp.29-34 |
| ICD, CPM |
2005-09-09
13:25 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Study of 6Gbps Operation on 0.18um Node CMOS I/O Inverter with Transmission Structure in Signal and Power Distribution Lines
Yutaka Akiyama (Meisei Univ.), Tsuneo Ito (Excel Service), Kyouji Ito (Renesas NJS), Kanji Otsuka (Meisei Univ.) |
This research acheeved measurement of the design which made transmission wiring for input and output to the 0.18um node ... [more] |
CPM2005-102 ICD2005-112
pp.35-40 |
| ICD, CPM |
2005-09-09
13:50 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Measurement of Inner-chip Variation and Signal Integrity By a 90-nm Large-scale TEG
Masaharu Yamamoto (STARC), Yayoi Hayasi, Hitoshi Endo (Hitachi ULSI), Hiroo Masuda (STARC) |
[more] |
CPM2005-103 ICD2005-113
pp.41-46 |
| ICD, CPM |
2005-09-09
14:30 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
[Invited Talk]
On chip transmission line interconnect
Kazuya Masu, Kenichi Okada, Hiroyuki Ito (Tokyo Institute of Technology) |
Recent Si CMOS performance becomes to be limited by the long global interconnect characteristics. In this paper, we dis... [more] |
CPM2005-104 ICD2005-114
pp.47-52 |
| SIP, ICD, IE, IPSJ-SLDM |
2005-10-20
09:00 |
Miyagi |
Ichinobo, Sakunami-Spa |
Measuring 3D Position Using Picture Angle
Jumpei Akabane, Kenji Ohmori (Hosei Univ.) |
[more] |
SIP2005-96 ICD2005-115 IE2005-60
pp.1-6 |
| SIP, ICD, IE, IPSJ-SLDM |
2005-10-20
09:20 |
Miyagi |
Ichinobo, Sakunami-Spa |
A Study of Ray-Space Coding Using a Hybrid Disparity Compensation DCT Codec
Kenji Yamamoto, Tomohiro Yendo, Toshiaki Fujii, Masayuki Tanimoto (Nagoya Univ.) |
This paper introduces how to adapt a hybrid DPCM/DCT Codec (HDDC) for ray information coding, based on the fact that the... [more] |
SIP2005-97 ICD2005-116 IE2005-61
pp.7-12 |
| SIP, ICD, IE, IPSJ-SLDM |
2005-10-20
09:40 |
Miyagi |
Ichinobo, Sakunami-Spa |
Temporal Segmentation of 3D Videos Based on Numerical Features
Toshihiko Yamasaki, Kiyoharu Aizawa (Univ. of Tokyo) |
3D video, which is generated from multi-viewpoint images, has been attracting increased attention because it can record ... [more] |
SIP2005-98 ICD2005-117 IE2005-62
pp.13-18 |
| SIP, ICD, IE, IPSJ-SLDM |
2005-10-20
10:00 |
Miyagi |
Ichinobo, Sakunami-Spa |
Detection of Ringing Distortion in Encoded Image by Wavelet Transform
Asako Toshihiro, Masashi Kameda (Iwate Prefectural Univ.) |
[more] |
SIP2005-99 ICD2005-118 IE2005-63
pp.19-24 |
| SIP, ICD, IE, IPSJ-SLDM |
2005-10-20
10:20 |
Miyagi |
Ichinobo, Sakunami-Spa |
Studies of the Shoeprint Coding Based on the Ridgelet-Hough Transform
-- A Proposition of Coding and Comparisons with the Conventional Method --
Makoto Hasegawa, Kazumoto Tanaka, Seiji Ishihara, Byon-chol So, Masakazu Kanezashi (Kinki Univ.), Hiroshi Moriwaki (Hiroshima Information Symphony) |
A shoeprint coding based on the ridgelet transform is proposed. The method of pattern matching using the Hough transform... [more] |
SIP2005-100 ICD2005-119 IE2005-64
pp.25-30 |
| SIP, ICD, IE, IPSJ-SLDM |
2005-10-20
10:50 |
Miyagi |
Ichinobo, Sakunami-Spa |
Analysis of low frequency component of signal by Generalized Harmonic Analysis (GHA)
Ichiyoh Maehara, Yoshihiro Kanda, Teruo Muraoka (Mi-TECH) |
Generalized Harmonic Analysis (GHA) that starts from fixed book of N.Wiener is being put to practical use by the sinusoi... [more] |
SIP2005-101 ICD2005-120 IE2005-65
pp.31-36 |
| SIP, ICD, IE, IPSJ-SLDM |
2005-10-20
11:10 |
Miyagi |
Ichinobo, Sakunami-Spa |
A Learning Algorithm Reducing Signal Distortion for Frequency Domain Feedforward Blind Source Separation
Yasuhiro Dejima, Akihide Horita, Kenji Nakayama, Akihiro Hirano (Kanazawa Univ.) |
[more] |
SIP2005-102 ICD2005-121 IE2005-66
pp.37-42 |
| SIP, ICD, IE, IPSJ-SLDM |
2005-10-20
11:30 |
Miyagi |
Ichinobo, Sakunami-Spa |
An Ultra-low Complexity Motion Estimation Algorithm and its Implementation of Specific Processor
Seiichiro Hiratsuka (Fukuoka IST), Satoshi Goto, Takeshi Ikenaga (Waseda Univ.) |
Motion estimation (ME) requires huge computation complexity. Many motion estimation algorithms have been proposed to red... [more] |
SIP2005-103 ICD2005-122 IE2005-67
pp.43-48 |
| SIP, ICD, IE, IPSJ-SLDM |
2005-10-20
11:50 |
Miyagi |
Ichinobo, Sakunami-Spa |
High-Quality Background Sprite Generation Based on Phase-Only Correlation
Norihito Numa, Takafumi Aoki (Tohoku Univ.), Satoshi Kondo (Matsushita Electric Industrial Co., Ltd.) |
A background sprite is an image composed of pixels belonging
to a video object visible throughout a video segment.
Thi... [more] |
SIP2005-104 ICD2005-123 IE2005-68
pp.49-54 |
| SIP, ICD, IE, IPSJ-SLDM |
2005-10-20
13:00 |
Miyagi |
Ichinobo, Sakunami-Spa |
A 2.0μm Pixel Pitch MOS Image Sensor with an Amorphous Si Film Color Filter
Masahiro Kasano, Yuichi Inaba, Mitsuyoshi Mori, Shigetaka Kasuga, Takahiko Murata, Takumi Yamaguchi (MEI) |
We have developed a 2.0 x 2.0 μm2 pixel size MOS image sensor with a high aperture ratio of 30%. The key technologies ar... [more] |
SIP2005-105 ICD2005-124 IE2005-69
pp.55-59 |
| SIP, ICD, IE, IPSJ-SLDM |
2005-10-20
13:20 |
Miyagi |
Ichinobo, Sakunami-Spa |
Four-Pixel accuracy Motion Estimation Unit using Extended Templates for HDTV Encording
Jin Kobayashi, Takahiro Hiramatsu, Takahiro Sasaki, Toshio Kondo (Mie Univ) |
This paper describes the design of a first-stage motion estimation unit using different extended templates for the hier... [more] |
SIP2005-106 ICD2005-125 IE2005-70
pp.61-66 |
| SIP, ICD, IE, IPSJ-SLDM |
2005-10-20
13:40 |
Miyagi |
Ichinobo, Sakunami-Spa |
A low power H.264 motion estimation algorithm for mobile video applications
Masaki Hamamoto, Kenichi Nagai (Kobe Univ.), Tetsuro Matsuno (Kanazawa Univ.), Yuichiro Murachi, Junichi Miyakoshi (Kobe Univ.), Masayuki Miyama (Kanazawa Univ.), Masahiko Yoshimoto (Kobe Univ.) |
H.264 employs variable block size motion compensation which supports 7 block sizes from 16x16 to 4x4. This feature enhan... [more] |
SIP2005-107 ICD2005-126 IE2005-71
pp.67-72 |
| SIP, ICD, IE, IPSJ-SLDM |
2005-10-20
14:00 |
Miyagi |
Ichinobo, Sakunami-Spa |
A Ray-Tracing Engine for Dynamic Scene Rendering
Yoshiyuki Kaeriyama, Kenichi Suzuki, Tadao Nakamura (Tohoku Univ.) |
[more] |
SIP2005-108 ICD2005-127 IE2005-72
pp.73-78 |
| SIP, ICD, IE, IPSJ-SLDM |
2005-10-20
14:30 |
Miyagi |
Ichinobo, Sakunami-Spa |
[Invited Talk]
A Psychologically-Inspired VLSI Brain Model System for Human-Like Image Recognition
Tadashi Shibata (Univ. of Tokyo) |
[more] |
SIP2005-109 ICD2005-128 IE2005-73
pp.79-87 |
| SIP, ICD, IE, IPSJ-SLDM |
2005-10-20
15:30 |
Miyagi |
Ichinobo, Sakunami-Spa |
A Memory Controller that Reduces Latency of Cached SDRAM
Seiji Miura, Satoru Akiyama (Hitachi,Ltd) |
The proposed controller has two main control schemes, address-alignment control and dummy-cache control scheme. These tw... [more] |
SIP2005-110 ICD2005-129 IE2005-74
pp.89-93 |
| SIP, ICD, IE, IPSJ-SLDM |
2005-10-20
15:50 |
Miyagi |
Ichinobo, Sakunami-Spa |
DFT Technique for Memory Macro with Built-in ECC
Keiichi Kushida, Nobuaki Otsuka, Osamu Hirabayashi, Yasuhisa Takeyama (Toshiba Co.) |
DFT techniques to implement ECC circuitry on
memory macro with no additional test cost are
proposed. New methodology t... [more] |
SIP2005-111 ICD2005-130 IE2005-75
pp.95-100 |
| SIP, ICD, IE, IPSJ-SLDM |
2005-10-20
16:10 |
Miyagi |
Ichinobo, Sakunami-Spa |
A Soft-Error-Immune TCAM Archiecture with Associated Embedded DRAM
Yuji Yano, Hideyuki Noda, Katsumi Dosaka, Fukashi Morishita, Kazunari Inoue, Toshiyuki Ogawa, Kazutami Arimoto (Renesas) |
[more] |
SIP2005-112 ICD2005-131 IE2005-76
pp.101-105 |
| SIP, ICD, IE, IPSJ-SLDM |
2005-10-20
16:30 |
Miyagi |
Ichinobo, Sakunami-Spa |
A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI
Takayuki Gyohten, Fukashi Morishita, Hideyuki Noda (Renesas Technology Corp.), Mako Okamoto (Daioh Electric Corp.), Takashi Ipposhi, Shigeto Maegawa, Katsumi Dosaka, Kazutami Arimoto (Renesas Technology Corp.) |
We propose a novel capacitorless twin-transistor random access memory (TTRAM). The 2Mb test device has been fabricated o... [more] |
SIP2005-113 ICD2005-132 IE2005-77
pp.107-112 |
| SIP, ICD, IE, IPSJ-SLDM |
2005-10-20
16:50 |
Miyagi |
Ichinobo, Sakunami-Spa |
A 333MHz Random Cycle DRAM Using the Floating Body Cell
Kosuke Hatsuda, Katsuyuki Fujita, Takashi Ohsawa (Toshiba Corp.) |
[more] |
SIP2005-114 ICD2005-133 IE2005-78
pp.113-118 |
| SIP, ICD, IE, IPSJ-SLDM |
2005-10-21
09:00 |
Miyagi |
Ichinobo, Sakunami-Spa |
A Phase Noise Minimization of CMOS LC-VCOs Over Wide Tuning Range and Large PVT Variations
Daisuke Miyashita, Hiroki Ishikuro, Shouhei Kousai, Hiroyuki Kobayashi, Hideaki Majima, Kenichi Agawa, Mototsugu Hamada (Toshiba Corp.) |
An automatic amplitude control circuit to minimize the phase noise of a LC-VCO is proposed and implemented by a 0.18-μm ... [more] |
SIP2005-115 ICD2005-134 IE2005-79
pp.1-5 |
| SIP, ICD, IE, IPSJ-SLDM |
2005-10-21
09:20 |
Miyagi |
Ichinobo, Sakunami-Spa |
Substrate Noise Reduction and Random Variability Neutralization with Self Adjusted Forward Body Bias Control
Yoshihide Komatsu, Koichiro Ishibashi, Toshiro Tsukada, Masaharu Yamamoto (STARC), Kenji Shimazaki, Mitsuya Fukazawa, Makoto Nagata (Kobe Univ.) |
[more] |
SIP2005-116 ICD2005-135 IE2005-80
pp.7-12 |
| SIP, ICD, IE, IPSJ-SLDM |
2005-10-21
09:40 |
Miyagi |
Ichinobo, Sakunami-Spa |
Thermal Analysis on Microprocessors
Naoyuki Hasegawa, Mutsuo Ito, Ryusuke Egawa, Kenichi Suzuki, Tadao Nakamura (Tohoku Univ.) |
Recently, the advance in the semiconductor process technology and the modern microarchitectural techniques have enabled ... [more] |
SIP2005-117 ICD2005-136 IE2005-81
pp.13-18 |
| SIP, ICD, IE, IPSJ-SLDM |
2005-10-21
10:10 |
Miyagi |
Ichinobo, Sakunami-Spa |
Development of an embedded processor core SH-X2
Takashi Okada (Hitachi), Tomoichi Hayashi, Takehiro Shimizu (Renesas), Fumio Arakawa, Tetsuya Yamada (Hitachi), Osamu Nishii, Toshihiro Hattori (Renesas) |
A {S}uper{H$^{\rm TM}$} embedded processor core, SH-X2 for consumer appliances, implemented in a 90-nm CMOS process runn... [more] |
SIP2005-118 ICD2005-137 IE2005-82
pp.19-24 |
| SIP, ICD, IE, IPSJ-SLDM |
2005-10-21
10:30 |
Miyagi |
Ichinobo, Sakunami-Spa |
Single-Chip Multi-Processor Integrating Quadruple 8-Way VLIW Processors
Atsushi Tanaka, Atsuhiro Suga, Fumihiko Hayakawa, Shinichiro Tago, Satoshi Imai (Fujitsu Lab) |
To realize the low power consumption and low-cost equipment needed to encode high-definition broadcasts, we have develo... [more] |
SIP2005-119 ICD2005-138 IE2005-83
pp.25-29 |
| SIP, ICD, IE, IPSJ-SLDM |
2005-10-21
10:50 |
Miyagi |
Ichinobo, Sakunami-Spa |
Compaction of Arithmetic Unit with Bit-Level-Parallelism
Jubee Tada (Yamagata Univ.), Ryusuke Egawa (Tohoku Univ.), Gensuke Goto (Yamagata Univ.), Tadao Nakamura (Tohoku Univ.) |
Aiming at reducing power consumption of VLSIs, we propose a fast and compact arithmetic unit. The arithmetic unit reduc... [more] |
SIP2005-120 ICD2005-139 IE2005-84
pp.31-35 |
| SIP, ICD, IE, IPSJ-SLDM |
2005-10-21
11:20 |
Miyagi |
Ichinobo, Sakunami-Spa |
[Invited Talk]
Development of Image Recognition Processor Based on Configurable Processor
Takashi Miyamori (Toshiba) |
We developed an image recognition processor, “Visconti,” based on a configurable processor. Three VLIW processors that e... [more] |
SIP2005-121 ICD2005-140 IE2005-85
pp.37-42 |
| SIP, ICD, IE, IPSJ-SLDM |
2005-10-21
13:00 |
Miyagi |
Ichinobo, Sakunami-Spa |
[Invited Talk]
Technology for Embedded Processors
Kunio Uchiyama (Hitachi) |
Embedded processors which are used in recent digital consumer appliances must satisfy the requirements of high-performan... [more] |
SIP2005-122 ICD2005-141 IE2005-86
pp.43-47 |
| SIP, ICD, IE, IPSJ-SLDM |
2005-10-21
14:00 |
Miyagi |
Ichinobo, Sakunami-Spa |
A Reliability Evaluation Technique for Soft-Error Susceptible Computer Systems
Makoto Sugihara (ISIT), Tohru Ishihara (Kyushu Univ.), Koji Hashimoto (Fukuoka Univ.), Masanori Muroyama (Kyushu Univ.) |
As the feature size of integrated circuits shrinks, their voltage and noise margins are lowered and the soft error issue... [more] |
SIP2005-123 ICD2005-142 IE2005-87
pp.49-54 |
| SIP, ICD, IE, IPSJ-SLDM |
2005-10-21
14:20 |
Miyagi |
Ichinobo, Sakunami-Spa |
A study for hardware optimization using a high level synthesis fron C
Satoru Inoue, Tsuyoshi Kondo, Tomonori Izumi, Masahiro Fukui (Rits) |
Higher abstraction design has been highly required so that a human can focus on inspired part of design by making comput... [more] |
SIP2005-124 ICD2005-143 IE2005-88
pp.55-60 |
| SIP, ICD, IE, IPSJ-SLDM |
2005-10-21
14:40 |
Miyagi |
Ichinobo, Sakunami-Spa |
A Cache-Defect-Aware Code Placement Technique for Improving the Performance of Processor
Tohru Ishihara (Kyushu Univ.), Farzan Fallah (FLA) |
[more] |
SIP2005-125 ICD2005-144 IE2005-89
pp.61-66 |
| SIP, ICD, IE, IPSJ-SLDM |
2005-10-21
15:00 |
Miyagi |
Ichinobo, Sakunami-Spa |
A study for power and speed tradeoff estimation for behavior hardware model
Noriyuki Inoue, Katsuhiro Oshikawa, Tomonori Izumi, Masahiro Fukui (Rits Univ.) |
Due to the increasing of the scale of systems, planning the design strategy based on the power estimation in early desig... [more] |
SIP2005-126 ICD2005-145 IE2005-90
pp.67-72 |
| SIP, ICD, IE, IPSJ-SLDM |
2005-10-21
15:30 |
Miyagi |
Ichinobo, Sakunami-Spa |
A Monitor Generation Method for Formal Monitor-based Verification Considering Input Constraints
Yosuke Kakiuchi (Osaka Univ.), Akira Kitajima (Osaka Electro-Communication Univ.), Kiyoharu Hamaguchi, Toshinobu Kashiwabara (Osaka Univ.) |
In order to verify hardware module interfaces, various verification methods have been proposed. This paper focuses on fo... [more] |
SIP2005-127 ICD2005-146 IE2005-91
pp.73-78 |
| SIP, ICD, IE, IPSJ-SLDM |
2005-10-21
15:50 |
Miyagi |
Ichinobo, Sakunami-Spa |
A cell library development methodology for character projection
Makoto Sugihara (ISIT), Taiga Takata, Kenta Nakamura (Kyushu Univ.), Ryoichi Inanami (e-BEAM), Hiroaki Hayashi (Tokyo Electron), Katsumi Kishimoto (e-BEAM), Tetsuya Hasebe (Tokyo Electron), Yukihiro Kawano (e-BEAM), Yusuke Matsunaga, Kazuaki Murakami (Kyushu Univ.), Katsuya Okumura (Univ. of Tokyo) |
We propose a cell library development methodology for throughput enhancement of electron beam direct-write (EBDW) system... [more] |
SIP2005-128 ICD2005-147 IE2005-92
pp.79-84 |
| SIP, ICD, IE, IPSJ-SLDM |
2005-10-21
16:10 |
Miyagi |
Ichinobo, Sakunami-Spa |
A Study for Power Grid Optimization
Taiki Harada, Kenji Kusano, Takayuki Shimada, Hironobu Ishijima, Masahiro Fukui (Rits Univ.) |
To the advent of super deep submicron age, stabilization of power supply system becomes more and more important against ... [more] |
SIP2005-129 ICD2005-148 IE2005-93
pp.85-90 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-11-30
13:30 |
Fukuoka |
Kitakyushu International Conference Center |
[Fellow Memorial Lecture]
Layout CAD and DFM
-- Beginning and Maturity --
Takashi Mitsuhashi (Cadence Japan) |
The auther had an opportunity to be engaged in development of VLSI layout design automation, and automation of design ve... [more] |
VLD2005-54 ICD2005-149 DC2005-31
pp.1-6 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-11-30
14:40 |
Fukuoka |
Kitakyushu International Conference Center |
40-Gbps 4:1 MUX/1:4 DEMUX in 90-nm standard CMOS technology
Kouichi Kanda, Daisuke Yamazaki, Takuji Yamamoto, Minoru Horinaka, Junji Ogawa, Hirotaka Tamura, Hiroyuki Onodera (Fujitsu Labs.) |
[more] |
VLD2005-55 ICD2005-150 DC2005-32
pp.7-14 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-11-30
15:05 |
Fukuoka |
Kitakyushu International Conference Center |
Enhancement of an Angular Position Error Measurement Circuit for Rotary Encoders
Teruo Tamama, , Tadashi Masuda (SIST) |
[more] |
VLD2005-56 ICD2005-151 DC2005-33
pp.15-20 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-11-30
15:30 |
Fukuoka |
Kitakyushu International Conference Center |
Low Power Design for IEEE 802.11 WLAN at the Medium Access Control Layer
EL Bourichi Adil, Hiroto Yasuura (Kyushu Univ.) |
[more] |
VLD2005-57 ICD2005-152 DC2005-34
pp.21-24 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-11-30
16:10 |
Fukuoka |
Kitakyushu International Conference Center |
Logic Synthesis Technique for High Speed Dynamic Logic with Asymmetric Slope Transition
Masao Morimoto, Makoto Nagata (Kobe Univ.), Kazuo Taki |
This paper proposes a logic synthesis technique for asymmetric slope differential dynamic logic (ASDDL) circuits. The te... [more] |
VLD2005-58 ICD2005-153 DC2005-35
pp.25-30 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-11-30
16:35 |
Fukuoka |
Kitakyushu International Conference Center |
A Discussion about Timing Signal Design Considering Delay Variation
Masashi Imai, Kouichi Watanabe, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya (Univ. Tokyo) |
As the VLSI technology advances, delay variations become extremely
large. There are many factors that cause delay varia... [more] |
VLD2005-59 ICD2005-154 DC2005-36
pp.31-36 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-11-30
17:00 |
Fukuoka |
Kitakyushu International Conference Center |
Design of High Performance and Low Power Arithmetic Circuits Considering Bit Delay Variation
Kouichi Watanabe, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya (Univ. Tokyo) |
As the VLSI technology advances, delay variations will become more serious.
Delay insensitive asynchronous dual-rail ci... [more] |
VLD2005-60 ICD2005-155 DC2005-37
pp.37-42 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-01
09:30 |
Fukuoka |
Kitakyushu International Conference Center |
Delay Testing for Application-Specific Interconnects of FPGAs based on Inphase Structure
Kosuke Yabuki, Satoshi Ohtake, Hideo Fujiwara (NAIST) |
This paper presents a method of path delay fault testing for application-specific interconnects in field-programmable ga... [more] |
VLD2005-61 ICD2005-156 DC2005-38
pp.1-6 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-01
09:55 |
Fukuoka |
Kitakyushu International Conference Center |
A equidistant transition circuit for detecting path-delay faults
Hyonsu Cho, Takeo Yoshida (Univ. of the Ryukyus) |
In this paper, we propose a equidistant transition circuit for detecting path delay faults. A value of each register in ... [more] |
VLD2005-62 ICD2005-157 DC2005-39
pp.7-12 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-01
10:20 |
Fukuoka |
Kitakyushu International Conference Center |
Reconfigurable Wrapper Design for Multi Clock Domain Cores Under Power Constraints
Yu Tanaka, Tomokazu Yoneda, Hideo Fujiwara (NAIST) |
This paper presents a re-configurable wrapper design for scan-designed multi-clock domain cores in system-on-chips. The ... [more] |
VLD2005-63 ICD2005-158 DC2005-40
pp.13-18 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-01
11:00 |
Fukuoka |
Kitakyushu International Conference Center |
Minimal Set of Essential Lifetime Overlaps for Exploring 3D Schedule
Mineo Kaneko (JAIST) |
[more] |
VLD2005-64 ICD2005-159 DC2005-41
pp.19-24 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-01
11:25 |
Fukuoka |
Kitakyushu International Conference Center |
A Consideration of Chaining methods on Behavioral Synthesis
Tsuyoshi Sadakata, Yusuke Matsunaga (Kyushu Univ.) |
In Behavioral Synthesis, operation chaining is one of the e±cient techniques to reduce the number of
control steps. Alm... [more] |
VLD2005-65 ICD2005-160 DC2005-42
pp.25-30 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-01
11:50 |
Fukuoka |
Kitakyushu International Conference Center |
A High-level Synthesis Algorithm Based on Floorplans for Distributed/Shared-Register Architectures
Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) |
[more] |
VLD2005-66 ICD2005-161 DC2005-43
pp.31-36 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-01
13:30 |
Fukuoka |
Kitakyushu International Conference Center |
Pipelined Bipartite Modular Multiplication
Marcelo E. Kaihara, Naofumi Takagi (Nagoya Univ.) |
[more] |
VLD2005-67 ICD2005-162 DC2005-44
pp.37-42 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-01
13:55 |
Fukuoka |
Kitakyushu International Conference Center |
no title
Keita Okubo, noname, noname, Takashi Kambe (noname) |
In the design of the arithmetic circuit for the embedded system, it is necessary to consider optimization of circuit sca... [more] |
VLD2005-68 ICD2005-163 DC2005-45
pp.43-48 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-01
14:20 |
Fukuoka |
Kitakyushu International Conference Center |
Consideration on Delay Estimation Methods for Prefix Graphs
Taeko Matsunaga (FLEETS), Yusuke Matsunaga (Kyushu Univ.) |
Prefix graph is an abstract representation of a parallel prefix adder and used to compare characteristics of various typ... [more] |
VLD2005-69 ICD2005-164 DC2005-46
pp.49-54 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-01
14:45 |
Fukuoka |
Kitakyushu International Conference Center |
Comparison of power consumption by form of adders
Takayuki Minakuchi, Shintaro Mimoto, Masayoshi Tachibana (KUT) |
We reported "Comparison of power consumption, area and speed by form of adders " at the VLSI design technical research m... [more] |
VLD2005-70 ICD2005-165 DC2005-47
pp.55-59 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-01
15:25 |
Fukuoka |
Kitakyushu International Conference Center |
A Study of the Model and the Accuracy of Statistical Timing Analysis
Izumi Nitta, Katsumi Homma, Toshiyuki Shibuya (Fujitsu Lab.) |
[more] |
VLD2005-71 ICD2005-166 DC2005-48
pp.61-66 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-01
15:50 |
Fukuoka |
Kitakyushu International Conference Center |
Fast Interconnect Delay Estimation with Considering Inductance Based on Multiple Regression Analysis
Kosei Suzuki, Marta D.Anwar, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) |
In recent DSM (Deep SubMicron) technology, we need to take some important points, such as floorplaning, interconnect res... [more] |
VLD2005-72 ICD2005-167 DC2005-49
pp.67-72 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-01
16:15 |
Fukuoka |
Kitakyushu International Conference Center |
Deterministic/Probablistic Noise and Bit Error Rate Modeling on On-chip Global interconnect
Yoichi Yuyama, Kazutoshi Kobayashi, Hidetoshi Onodera (Kyoto Univ.) |
[more] |
VLD2005-73 ICD2005-168 DC2005-50
pp.73-78 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-01
16:40 |
Fukuoka |
Kitakyushu International Conference Center |
Timing-Driven Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization
Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada (Univ. of Tokyo) |
[more] |
VLD2005-74 ICD2005-169 DC2005-51
pp.79-84 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-01
17:05 |
Fukuoka |
Kitakyushu International Conference Center |
Floorplan Design for 3D-VLSI
Hidenori Ohta (Tokyo Univ. of Agri. & Tech.), Toshinori Yamada (Saitama Univ.), Chikaaki Kodama, Kunihiro Fujiyoshi (Tokyo Univ. of Agri. & Tech.) |
[more] |
VLD2005-75 ICD2005-170 DC2005-52
pp.85-90 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-02
09:30 |
Fukuoka |
Kitakyushu International Conference Center |
On Low Capture Power Test Generation for Scan Testing
Tatsuya Suzuki, Xiaoqing Wen, Seiji Kajihara (K.I.T.), Kohei Miyase, Yoshihiro Minamoto (JST) |
High switching activity occurs when the response to a test vector is captured by flip-flops during scan testing. This ma... [more] |
VLD2005-76 ICD2005-171 DC2005-53
pp.1-6 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-02
09:55 |
Fukuoka |
Kitakyushu International Conference Center |
A Broadside Test Generation Method for Transition Faults in Partial Scan Circuits
Tsuyoshi Iwagaki (JAIST), Satoshi Ohtake, Hideo Fujiwara (NAIST) |
This paper presents a broadside test generation method for
transition faults in partial scan circuits. In order to gene... [more] |
VLD2005-77 ICD2005-172 DC2005-54
pp.7-12 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-02
10:20 |
Fukuoka |
Kitakyushu International Conference Center |
A Note on Expansion of Convolutional Compactors on Galois Field
Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki (Tokyo Metro. Univ.) |
Convolutional compactors offer a promising technique of compacting test responses. In this study we expand the architect... [more] |
VLD2005-78 ICD2005-173 DC2005-55
pp.13-18 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-02
11:00 |
Fukuoka |
Kitakyushu International Conference Center |
Handling of Variables and Functions for Software Compatible Hardware Synthesizer CCAP
Kenichi Nishiguchi, Nagisa Ishiura, Masanari Nishimura (Kwansei Gakuin Univ.), Hiroyuki Kanbara (ASTEM), Hiroyuki Tomiyama (Nagoya Univ.), Yutetsu Takatsukasa, Manabu Kotani (Kyoto Univ.) |
We are developing a high-level synthesis tool named CCAP (C Compatible Architecture Prototyper), which synthesizes arbit... [more] |
VLD2005-79 ICD2005-174 DC2005-56
pp.19-24 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-02
11:25 |
Fukuoka |
Kitakyushu International Conference Center |
A Method for Allocating Bus Transfer and Task Execution Cycles Based on Scenarios
Seiji Yamaguchi, Tadaaki Tanimoto, Akio Nakata, Teruo Higashino (Osaka Univ.) |
In designing a bus system, it is important to derive a real-time constraint (the number of available cycles) for each ta... [more] |
VLD2005-80 ICD2005-175 DC2005-57
pp.25-30 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-02
11:50 |
Fukuoka |
Kitakyushu International Conference Center |
no title
Kenichi Jyoko, Takahiro Ohguchi, Hirokazu Uetsu, Koji Sakai, noname, Takashi Kambe (noname) |
[more] |
VLD2005-81 ICD2005-176 DC2005-58
pp.31-36 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-02
13:30 |
Fukuoka |
Kitakyushu International Conference Center |
Examinations of Small-World and Scale-Free characteristics in logic circuits
Toshiaki Miyazaki (Univ. of Aizu) |
Recently, it has been reported that many networks existing in both
natural and artificial things have the Small-World ... [more] |
VLD2005-82 ICD2005-177 DC2005-59
pp.37-40 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-02
13:55 |
Fukuoka |
Kitakyushu International Conference Center |
Exact Minimum Factoring via Quantified Boolean Satisfiability
Hiroaki Yoshida, Makoto Ikeda, Kunihiro Asada (Univ. of Tokyo) |
[more] |
VLD2005-83 ICD2005-178 DC2005-60
pp.41-46 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-02
14:20 |
Fukuoka |
Kitakyushu International Conference Center |
An Encoding Method for Rail Outputs in LUT Cascade Emulators
Shinya Nagayasu, Tsutomu Sasao, Munehiro Matsuura (KIT) |
[more] |
VLD2005-84 ICD2005-179 DC2005-61
pp.47-52 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-02
14:45 |
Fukuoka |
Kitakyushu International Conference Center |
A Logic Simulation using an LUT Cascade Emulator
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (KIT) |
This paper shows a cycle-based logic simulation method using an LUT cascade emulator.
The LUT cascade emulator is an ar... [more] |
VLD2005-85 ICD2005-180 DC2005-62
pp.53-58 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-02
15:25 |
Fukuoka |
Kitakyushu International Conference Center |
Efficient contraction of timed signal transition graphs
Tomohiro Yoneda (NII), Chris Myers (Univ. of Utah) |
In the decomposition based synthesis method, for each output signal,
an input signal set sufficient to synthesize a cir... [more] |
VLD2005-86 ICD2005-181 DC2005-63
pp.59-64 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-02
15:50 |
Fukuoka |
Kitakyushu International Conference Center |
Structural Coverage of Traversed Transitions for Symbolic Model Checking
Xingwen Xu, Shinji Kimura (Waseda Univ.), Kazunari Horikawa, Takehiko Tsuchiya (Toshiba) |
Coverage estimation for model checking has become an important issue in practical formal verification. Transition traver... [more] |
VLD2005-87 ICD2005-182 DC2005-64
pp.65-70 |
| ICD |
2005-12-15
10:30 |
Kochi |
|
[Special Invited Talk]
Dynamically Reconfigurable Processor DRP and its C based Design Environment
Toru Awashima (NEC) |
A C Compiler for Dynamically Reconfigurable Processor: DRP is presented. Software like design environment is realized by... [more] |
ICD2005-183
pp.1-6 |
| ICD |
2005-12-15
11:20 |
Kochi |
|
Scalable Bus Interface for HSDPA Co-processor Extension
Toshiki Takeuchi, Hiroyuki Igura (NEC), Takeshi Hashimoto (NECEL), Soichi Tsumura, Naoki Nishi (NEC) |
This paper presents a scalable bus developed for HSDPA co-processor extension of W-CDMA digital baseband processors. The... [more] |
ICD2005-184
pp.7-11 |
| ICD |
2005-12-15
11:45 |
Kochi |
|
VLSI Processor Architecture Based on Intra-Chip Packet Data Transfer Scheme
Yoshichika Fujioka, Nobuhiro Tomabechi (Hachinohe Inst. of Tech.), Michitaka Kameyama (Tohoku Univ.) |
[more] |
|
| ICD |
2005-12-15
13:00 |
Kochi |
|
[Special Invited Talk]
Multiprocessor Architecture on Integrated Platform for Digital Consumer Electronics
Yoshito Nishimichi, Kozo Kimura, Masaitsu Nakajima, Tokuzo Kiyohara (Matsushita Electric) |
[more] |
ICD2005-185
pp.13-17 |
| ICD |
2005-12-15
13:50 |
Kochi |
|
A DVFS Method for High-Performance and Low-Power Chip Multiprocessors
Masaaki Kondo, Hiroshi Nakamura (Univ. of Tokyo) |
[more] |
ICD2005-186
pp.19-24 |
| ICD |
2005-12-15
14:15 |
Kochi |
|
Adaptive Instruction Cascading on GALS Microprocessors
Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura (Univ. of Tokyo) |
As difficulty and the costs of distributing a single global clock throughout a processor is growing generation by genera... [more] |
ICD2005-187
pp.25-30 |
| ICD |
2005-12-15
14:40 |
Kochi |
|
Development of a Special-Purpose Processor for Molecular Orbital Calculations
Kenta Nakamura, Hiroaki Honda, Koji Inoue, Kazuaki Murakami (Kyushu Univ.) |
[more] |
ICD2005-188
pp.31-36 |
| ICD |
2005-12-15
15:15 |
Kochi |
|
Evaluation of energy consumption for High-Performance / Low-Leakage Caches based on Always Active line
Reiko Komiya (Fukuoka Univ.), Koji Inoue, Kazuaki Murakami (Kyushu Univ.) |
So far we proposed a cache management technique to alleviate the negative effect of low-leakage caches. This technique m... [more] |
ICD2005-189
pp.37-42 |
| ICD |
2005-12-15
15:40 |
Kochi |
|
Performance/Power Analysis of A Secure Cache Architecture for Buffer-Overflow Prevention
Koji Inoue (Kyushu Univ.) |
[more] |
ICD2005-190
pp.43-48 |
| ICD |
2005-12-15
16:05 |
Kochi |
|
[Special Invited Talk]
Entrepreneur engineering
-- A new concept of engineering education --
Osamu Tomisawa, Gota Kano (KUT) |
Management education for engineering people who work in actual companies has become important these days. Specifically, ... [more] |
ICD2005-191
pp.49-54 |
| ICD |
2005-12-16
09:00 |
Kochi |
|
Ultra Small Random Number Generator for Information Security
Shinichi Yasuda, Tetsufumi Tanamoto, Ryuji Ohba, Keiko Abe, Hanae Nozaki, Shinobu Fujita (Toshiba Corp.) |
We present small random number generators using silicon devices that generate large fluctuating signal as noise source d... [more] |
ICD2005-192
pp.1-6 |
| ICD |
2005-12-16
09:25 |
Kochi |
|
Design of Immune Algorithm Accelerator
Tsuyoshi Ozeki, Masaya Yoshikawa, Hidekazu Terai (Ritsumeikan Univ.) |
[more] |
ICD2005-193
pp.7-12 |
| ICD |
2005-12-16
09:50 |
Kochi |
|
A Low Dynamic Power and Low Leakage Power 90-nm CMOS Clock Driver
Suguru Nagayama, Tadayoshi Enomoto (Chuo Univ.) |
A technique, which can minimize not only an active power (Pat) and an stand-by power (Pst) but also a delay time (td) of... [more] |
ICD2005-194
pp.13-18 |
| ICD |
2005-12-16
10:15 |
Kochi |
|
Low-Power High-Speed Reduced-Clock-Swing Flip-Flops Based on Contention Reduction Techniques
Muhammad Yazid, Hiroshi Kawaguchi, Takayasu Sakurai (Tokyo Univ.) |
A new flip-flop circuit is proposed for use in the reduced swing clock environment. Simulations were done and it was fou... [more] |
ICD2005-195
pp.19-24 |
| ICD |
2005-12-16
10:50 |
Kochi |
|
A Conditional Clocking Flip-Flop for Low Power H.264/MPEG-4 Audio/Visual Codec LSI
Mototsugu Hamada, Hiroyuki Hara, Tetsuya Fujita, Chen Kong Teh, Takayoshi Shimazawa, Naoyuki Kawabe, Takeshi Kitahara, Yu Kikuchi, Tsuyoshi Nishikawa, Masafumi Takahashi, Yukihito Oowaki (Toshiba Corp.) |
A novel conditional clocking flip-flop is proposed. The flip-flop circuit does not consume any power when the data inpu... [more] |
ICD2005-196
pp.25-29 |