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Technical Committee on VLSI Design Technologies (VLD)  (Searched in: 2010)

Search Results: Keywords 'from:2011-03-02 to:2011-03-02'
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Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Ascending)
 Results 21 - 32 of 32 [Previous]  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD 2011-03-03
16:30		 Okinawa Okinawaken-Danjo-Kyodo-Sankaku Center Delay Analysis of Sub-Path on Fabricated Chips by Several Path-delay Tests
Takanobu Shiki, Yasuhiro Takashima (Univ.of Kitakyushu), Yuichi Nakamura (NEC Corp.) VLD2010-136		  [more] VLD2010-136
pp.117-122
VLD 2011-03-04
10:00		 Okinawa Okinawaken-Danjo-Kyodo-Sankaku Center A Routing Method for Multi-Layer Single Flux Quantum Circuits with Wire Ordering based on Slack Allocation
Shota Takeshima, Kazuyoshi Takagi, Masamitsu Tanaka (Nagoya Univ.), Naofumi Takagi (Kyoto Univ.) VLD2010-137		  [more] VLD2010-137
pp.123-128
VLD 2011-03-04
10:25		 Okinawa Okinawaken-Danjo-Kyodo-Sankaku Center CRP : Efficient Topology Modification for Minimum Perturbation Placement Realization
Yuki Kouno, Yasuhiro Takashima (Univ. of Kitakyushu), Atsushi Takahashi (Osaka Univ.) VLD2010-138		  [more] VLD2010-138
pp.129-134
VLD 2011-03-04
10:50		 Okinawa Okinawaken-Danjo-Kyodo-Sankaku Center Fast Algorithm for All-Pair Shortest Path on DAG using CUDA
Akihide Yamamura, Yasuhiro Takashima (Univ. of Kitakyushu) VLD2010-139		 (To be available after the conference date) [more] VLD2010-139
pp.135-139
VLD 2011-03-04
11:15		 Okinawa Okinawaken-Danjo-Kyodo-Sankaku Center On Realization and Evaluation of Capacitors in Analog Integrated Circuits
Atsushi Ochi, Ryoei Shimazu, Toru Fujimura, Shigetoshi Nakatake (Univ.of Kitakyushu) VLD2010-140		 As proceeding to a deep submicron era,
the area efficiency of and the precision of passive components have become
impo... [more]		 VLD2010-140
pp.141-146
VLD 2011-03-04
13:10		 Okinawa Okinawaken-Danjo-Kyodo-Sankaku Center An evaluation of error detection/correction circuits by gate level simulation
Masafumi Inoue (Tokyo Tech.), Yuuta Ukon, Atsushi Takahashi (Osaka Univ.) VLD2010-141		 In a typical synchronous circuit design, the maximum delay between flip-flops gives a lower bound of the clock period su... [more] VLD2010-141
pp.147-152
VLD 2011-03-04
13:35		 Okinawa Okinawaken-Danjo-Kyodo-Sankaku Center Behavior Verification of a Variable Latency Circuit on FPGA
Yuuta Ukon (Osaka Univ), Masafumi Inoue (Tokyo Tech), Atsushi Takahashi, Kenji Taniguchi (Osaka Univ) VLD2010-142		  [more] VLD2010-142
pp.153-158
VLD 2011-03-04
14:00		 Okinawa Okinawaken-Danjo-Kyodo-Sankaku Center Acceleration of Bounded Model Checking for Sequential Circuits with Two-phase Verification
Norihiro Ono, Kazuhiro Nakamura, Kazuyoshi Takagi (Nagoya Univ.), Naofumi Takagi (Kyoto Univ.) VLD2010-143		  [more] VLD2010-143
pp.159-164
VLD 2011-03-04
14:25		 Okinawa Okinawaken-Danjo-Kyodo-Sankaku Center Write Optimization for High-speed Non-volatile Memory Using Next State Function
Naoya Okada (Waseda Univ.), Yuichi Nakamura (NEC), Shinji Kimura (Waseda Univ.) VLD2010-144		 Non-volatile memory, such as MRAM and PCM, attracts attention for reducing power consumption. However, it consumes large... [more] VLD2010-144
pp.165-170
VLD 2011-03-04
15:05		 Okinawa Okinawaken-Danjo-Kyodo-Sankaku Center A scalable prototyping system for 3D-stacked LSI development
Marco Chacin, Hiroyuki Uchida, Michiya Hagimoto, Takashi Miyazaki, Takeshi Ohkawa, Rimon Ikeno, Yukoh Matsumoto (TOPS Systems), Fumito Imura, Katsuya Kikuchi, Motohiro Suzuki, Hiroshi Nakagawa, Masahiro Aoyagi (AIST) VLD2010-145		 (To be available after the conference date) [more] VLD2010-145
pp.171-175
VLD 2011-03-04
15:30		 Okinawa Okinawaken-Danjo-Kyodo-Sankaku Center Performance Evaluation of Via Programmable ASIC Architecture VPEX3
Taisuke Ueoka, Tatsuya Kitamori, Ryohei Hori (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.), Takeshi Fujino (Ritsumeikan Univ.) VLD2010-146		 We have been studying via programmable ASIC architecture “VPEX” whose logic element (LE) consists of complex-gate type E... [more] VLD2010-146
pp.177-182
VLD 2011-03-04
15:55		 Okinawa Okinawaken-Danjo-Kyodo-Sankaku Center Evaluation of Wiring Resource and Wiring Delay used in Via Programmable Logic Device VPEX
Tatsuya Kitamori, Ryohei Hori, Taisuke Ueoka (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.), Takeshi Fujino (Ritsumeikan Univ.) VLD2010-147		 We have developed a via programmable logic device using exclusive-or array (VPEX). In a VPEX, the logic is changed using... [more] VLD2010-147
pp.183-188
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