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Technical Committee on VLSI Design Technologies (VLD) (Searched in: 2010)
Search Results: Keywords 'from:2011-03-02 to:2011-03-02'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD | 2011-03-02 13:10 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | An Architecture Exploration Method based on a Branch-and-Bound Strategy for Embedded VLIW Processors Kohei Aoki, Ittetsu Taniguchi, Hiroyuki Tomiyama, Masahiro Fukui (Ritsumeikan Univ.)  VLD2010-116 |
This paper proposes an architecture exploration method based on a branch-and-bound strategy for embedded VLIW processors... [more] | VLD2010-116 pp.1-6 |
| VLD | 2011-03-02 13:35 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | Energy-Aware Instruction Scheduling for Fine-Grained Power-Gated VLIW Processors with Multi-Cycle Instructions Mitsuya Uchida, Ittetsu Taniguchi, Hiroyuki Tomiyama, Masahiro Fukui (Ritsumeikan Univ.) VLD2010-117 |
Reducing energy consumption is a crucial for the embedded system design, and especially, the leakage energy reduction is... [more] | VLD2010-117 pp.7-12 |
| VLD | 2011-03-02 14:00 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | Exact, Fast and Flexible Two-level Cache Simulation for Embedded Systems Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa (Waseda Univ.) VLD2010-118 |
In hierarchical cache configurations, L1 cache uses LRU as cache replacement policy but L2 and/or L3 caches use FIFO du... [more] |
VLD2010-118 pp.13-18 |
| VLD | 2011-03-02 14:25 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | Intra-task Analysis of Worst Case Execution Time and Average Energy Consumption on DEPS Framework Hirotaka Kawashima, Gang Zeng, Noritoshi Atsumi, Tomohiro Tatematsu, Hiroaki Takada (Nagoya Univ.) VLD2010-119 |
In this paper, we show an intra-task average energy consumption(AEC) and worst case execution time(WCET) analysis. The ... [more] | VLD2010-119 pp.19-24 |
| VLD | 2011-03-02 15:05 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | An Energy-efficient ASIP Synthesis Method Using Scratchpad Memory and Code Placement Optimization Yoshinori Shimada, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2010-120 |
In this paper, we propose an energy-efficient ASIP synthesis method using scratchpad memory. Due to the fact that a si... [more] |
VLD2010-120 pp.25-30 |
| VLD | 2011-03-02 15:30 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | Investigation and Evaluation of Sleep Signal Control based on a History Information for Fine-grain Power Gating Tetsuya Muto, Kimiyoshi Usami (Shibaura Inst. of Tech.) VLD2010-121 |
In Fine-grain Power Gating which reduces the leakage power by cutting Power Supply, Break Even Time(BET) which is the ti... [more] | VLD2010-121 pp.31-36 |
| VLD | 2011-03-02 15:55 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | Low Power Design of Digital Circuits using Quasi-complementary MOS Gates Shuichi Sowa, Mineo Kaneko (JAIST) VLD2010-122 |
It is prerequisite for LSI design to consider the power consumption, because of the rapid increase of the power consumpt... [more] | VLD2010-122 pp.37-42 |
| VLD | 2011-03-02 16:20 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | Reusable Constraints of Nano-watt BGR Circuits in CMOS Process Migration Gong Chen, Delong Yin, Bo Yang, Qing Dong, Jing Li, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2010-123 |
[more] | VLD2010-123 pp.43-47 |
| VLD | 2011-03-02 17:00 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | [Fellow Memorial Lecture]
Understanding CMOS Variability for More Moore Hidetoshi Onodera (Kyoto Univ./JST) VLD2010-124 |
With the device dimensions in the nanometer regime, variability becomes a serious concern in LSI design. Aggressive sc... [more] |
VLD2010-124 p.49 |
| VLD | 2011-03-03 09:55 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | Semi-static TSPC DFF Using Split-output Latch Tomoyuki Nakabayashi, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo (Mie Univ.) VLD2010-125 |
DFFs play important roles in the CMOS circuits because the performance of DFFs significantly affects the area and the p... [more] |
VLD2010-125 pp.51-56 |
| VLD | 2011-03-03 10:20 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | Implementation and Security Evaluation of DPA-Resistant DES Circuit utilizing Domino-RSL technique Katsuhiko Iwai, Kenji Kojima, Mitsuru Shiozaki, Syunsuke Asagawa, Takeshi Fujino (Ritsumeikan Univ.) VLD2010-126 |
Some secure DPA-resistant techniques to protect from Side-Channel Attack such as Differential Power Analysis (DPA) have ... [more] | VLD2010-126 pp.57-62 |
| VLD | 2011-03-03 10:45 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | Evaluation of Delay-Time Difference Distribution for the Delay-Time Difference Measurable Arbiter-PUF Takahiko Murayama, Mitsuru Shiozaki, Kota Furuhashi, Akitaka Fukushima, Takeshi Fujino (Ritsumeikan Univ.) VLD2010-127 |
Physical Unclonable Functions (PUFs) have been proposed to produce tamper-resistant device or create unique identificati... [more] | VLD2010-127 pp.63-68 |
| VLD | 2011-03-03 11:25 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | A Low Power Hardware Architecture for Parallel Group Signature Computation Sumio Morioka, Jun Furukawa, Kazue Sako (NEC) VLD2010-128 |
We've investigated architecture of H/W accelerators for parallel group signature computation, which will be used in data... [more] | VLD2010-128 pp.69-74 |
| VLD | 2011-03-03 11:50 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | A scalable hardware architecture for real time image recognition Takashi Aoki, Eiichi Hosoya, Takuya Otsuka, Akira Onozawa (NTT) VLD2010-129 |
A scalable hardware architecture is proposed for real time image recognition application. The hardware creates feature... [more] |
VLD2010-129 pp.75-80 |
| VLD | 2011-03-03 13:45 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | A Circuit Synthesis for High Speed Memory Access in System LSI Kazuya Kishida, Takashi Kambe (Kinki Univ.) VLD2010-130 |
In system LSI, large-scale data is accessed from off-chip memory in many cases, and the architecture design of the memor... [more] | VLD2010-130 pp.81-86 |
| VLD | 2011-03-03 14:10 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | A Circuit Synthesis for Dynamic Reconfigurable Processor Nobuyuki Araki, Takashi Kambe (Kinki Univ.) VLD2010-131 |
Dynamic reconfiguraible processors can implement large-scale and complicated circuits by changing its configurations dur... [more] | VLD2010-131 pp.87-92 |
| VLD | 2011-03-03 14:35 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | A Circuit Design and Its Evaluation for Correlation Caluculation in Particle Tracking System Shouta Moriguchi, Takashi Kambe (Kinki Univ.) VLD2010-132 |
Although particle-tracking method is useful for various kinds of flow analysis, its processing time is large. In this pa... [more] | VLD2010-132 pp.93-98 |
| VLD | 2011-03-03 15:00 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | Delay Variation-Aware Datapath Synthesis for Improved Performance and Tunability Dang Yu, Mineo Kaneko (JAIST) VLD2010-133 |
[more] | VLD2010-133 pp.99-104 |
| VLD | 2011-03-03 15:40 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | A Study for Evaluation of Statistical Maximum Operations for Gaussian Mixture Models Tamotsu Ishihara, Masahiro Fukui (Ritsumeikan Univ.), Shuji Tsukiyama (Chuo Univ.) VLD2010-134 |
In order to improve the accuracy of statistical static timing analysis, a method using Gaussian mixture models have been... [more] | VLD2010-134 pp.105-110 |
| VLD | 2011-03-03 16:05 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | Performance Evaluation of Statistical Static Timing Analysis Using Gaussian Mixture Models Tomoyuki Fujimori, Shuji Tsukiyama (Chuo Univ), Masahiro Fukui (Ritsumeikan Univ) VLD2010-135 |
With the progress of micro-technology, the within die process variability is increasing, and the statistical static timi... [more] | VLD2010-135 pp.111-116 |
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