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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| RECONF | 2013-09-19 13:00 |
Ishikawa | Japan Advanced Institute of Science and Technology | The Circuit Configuration method of 3D FPGA-Array System "Vocalise" Hiromasa Kubo, Jiang Li, Yusuke Atsumari, Baku Ogasawara, Masatoshi Sekine (Tokyo Univ. of Agliculture and Tech.)  RECONF2013-32 |
We have been developing the 3D FPGA-Array HPC system named as“Vocalise(Virtual Object by Configurable Array of Little Sc... [more] | RECONF2013-32 pp.73-78 |
| SDM, ICD | 2013-08-02 13:00 |
Ishikawa | Kanazawa University | A 0.4-1V SAR ADC Using Wide Range Operation Asynchronous Controller Yosuke Toyama, Akira Shikata, Kentaro Yoshioka, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro (Keio Univ.) SDM2013-80 ICD2013-62 |
This paper presents a wide range in supply voltage, resolution, and sampling rate asynchronous successive approximation ... [more] | SDM2013-80 ICD2013-62 pp.77-82 |
| DC | 2013-06-21 16:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | An Online Interconnect Test of SoC with Boundary Scan Shift and Embedded Reconfigurable Core Kentaroh Katoh (TNCT) DC2013-14 |
This paper presents an online Interconnect test of SoC with Boundary Scan Shift and embedded reconfigurable core. The pr... [more] | DC2013-14 pp.25-29 |
| RECONF | 2013-05-21 10:35 |
Kochi | Kochi Prefectural Culture Hall | Implementation of Speculative Gather System for CMA Rie Uno, Nobuaki Ozaki, Mai Izawa, Akihito Tsusaka, Takaaki Miyajima, Hideharu Amano (Keio Univ.) RECONF2013-11 |
Cool Mega Array (CMA) is a low power reconfigurable processor array for battery driven mobile devices. A prototype chip ... [more] | RECONF2013-11 pp.55-60 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] | 2013-03-14 09:10 |
Nagasaki | Guarantee of finising of calculate for a low power accelerator CMA Akihito Tsusaka, Mai Izawa, Rie Uno, Nobuaki Ozaki, Hideharu Amano (Keio Univ.) CPSY2012-86 DC2012-92 |
Cool Mega-Array (CMA) is a novel high performance but low power reconfigurable accelerator consisting of a large PE (Pr... [more] |
CPSY2012-86 DC2012-92 pp.205-210 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 17:00 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | [Keynote Address]
Dynamically Reconfigurable Processor (DRP) Technology: Current Status and Future Prospects Masato Motomura (Hokkaido Univ.), Koichiro Furuta, Toru Awashima, Yasunari Shida (Renesas Electronics) VLD2012-87 CPM2012-117 ICD2012-81 CPSY2012-55 DC2012-53 RECONF2012-49 |
DRP features two dimensional array of tiny processors and memories, onto which applications are compiled and mapped as a... [more] | VLD2012-87 CPM2012-117 ICD2012-81 CPSY2012-55 DC2012-53 RECONF2012-49 p.163(VLD), p.29(CPM), p.29(ICD), p.45(CPSY), p.163(DC), p.15(RECONF) |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-28 13:25 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | A 3D FPGA-Array HPC System "Vocalise" and its Performance Evaluation Yusuke Atsumari, Jiang Li, Hiromasa Kubo, Hakaru Tamukoh, Masatoshi Sekine (TUAT) VLD2012-94 DC2012-60 |
We have developed a 10cm square card with a three-dimensional I/O that installed a 4 million system gate scale FPGA and ... [more] | VLD2012-94 DC2012-60 pp.201-206 |
| RECONF | 2012-09-18 10:20 |
Shiga | Epock Ritsumei 21, Ritsumeikan Univ. | JPEG encoder design improvement and its evaluation for Dynamic Reconfigurable Circuit Hajime Sawano, Nobuyuki Araki, Takashi Kambe (Kinki Univ.) RECONF2012-26 |
Reconfigurable Computing (RC) has been proposed as a new paradigm to address the conflicting design requirements of high... [more] | RECONF2012-26 pp.13-18 |
| SR | 2012-05-24 17:15 |
Kanagawa | Keio univ. at Hiyoshi | [Panel Discussion]
Multi-band operation for mobile terminals Shoichi Narahashi, Hiroshi Okazaki, Atsushi Fukuda, Takayuki Furuta, Kunihiro Kawai, Kei Satoh, Yuta Takagi (NTT DOCOMO) SR2012-12 |
It is a key issue for radio frequency (RF) circuits of future mobile terminals to equip with multi-band operation archit... [more] | SR2012-12 pp.73-78 |
| VLD | 2012-03-07 13:20 |
Oita | B-con Plaza | Power reduction of memory circuit and DVFS technique in Dynamic Reconfigurable Processor Yuki Hayakawa, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2011-138 |
This paper describes a DVFS technique to reduce energy dissipation of Dynamically Reconfigurable Processors(DRP). DRP’s ... [more] | VLD2011-138 pp.109-114 |
| VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2012-01-26 14:20 |
Kanagawa | Hiyoshi Campus, Keio University | Implementation of Numerical Circuit on 3D FPGA-Array Kenichi Takahashi, Jiang Li, Yusuke Atsumari, Shunsuke Shimazaki, Hakaru Tamukoh, Masatoshi Sekine (TUAT) VLD2011-115 CPSY2011-78 RECONF2011-74 |
In recent years, High Performance Computing (HPC) is increasingly used in various fields. HPC systems require both the f... [more] | VLD2011-115 CPSY2011-78 RECONF2011-74 pp.141-146 |
| VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2012-01-26 16:40 |
Kanagawa | Hiyoshi Campus, Keio University | Study of pattern area and reconfigurable logic circuit with DG/CNT transistor Takamichi Hayashi, Shigeyoshi Watanabe (SIT) VLD2011-119 CPSY2011-82 RECONF2011-78 |
Pattern area for 2~6 input reconfigurable logic circuit with double-gate (DG), Carbon-Nano-Tube (CNT), double-gate and C... [more] | VLD2011-119 CPSY2011-82 RECONF2011-78 pp.163-168 |
| RECONF | 2011-09-27 11:25 |
Aichi | Nagoya Univ. | A proposal of pattern matching techniques using dynamically reconfigurable hardware Masato Nogami, Nobuya Watanabe, Akira Nagoya (Okayama Univ.) RECONF2011-37 |
The pattern matching of the strings using hardware has the problem that increases circuit size when the number of patter... [more] | RECONF2011-37 pp.87-92 |
| RECONF | 2011-09-27 13:20 |
Aichi | Nagoya Univ. | Design and Implementation of Adaptive Viterbi Decoder using Dynamic Reconfigurable System STP Engine Yuken Kishimoto, Takao Toi, Takaaki Miyajima, Hideharu Amano (Keio Univ.) RECONF2011-38 |
Implementing Viterbi Algorithm that is the decoding method of Convolutional code on hard-wired logic, in order to variou... [more] | RECONF2011-38 pp.93-98 |
| SDM, ICD | 2011-08-25 09:50 |
Toyama | Toyama kenminkaikan | Study of pattern area for reconfigurable logic circuit with DG/CNT transistor Takamichi Hayashi, Shigeyoshi Watanabe (SIT) SDM2011-73 ICD2011-41 |
Pattern area for 2~6 input reconfigurable logic circuit with double-gate (DG), Carbon-Nano-Tube (CNT), double-gate and C... [more] | SDM2011-73 ICD2011-41 pp.13-16 |
| SCE | 2011-07-13 15:40 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | High-Throuput Bit-Slice Multipliers Using SFQ Circuits Yohei Naruse, Nobutaka Kito, Naofumi Takagi (Kyoto Univ.) SCE2011-9 |
Single flux quantum (SFQ) circuits are expected as next-generation circuits. Arithmetic circuits using SFQ circuits have... [more] | SCE2011-9 pp.47-52 |
| SIS | 2011-03-03 10:50 |
Tokyo | Tokyo City University (Setagaya Campus) | Dynamically reconfigurable platform for self-organizing neural networks Hakaru Tamukoh, Masatoshi Sekine (TUAT) SIS2010-55 |
In this paper, we propose a dynamically reconfigurable platform for self-organizing neural network hardware. In the pro... [more] |
SIS2010-55 pp.13-17 |
| CS, SIP, CAS | 2011-03-03 10:50 |
Okinawa | Ohhamanobumoto memorial hall (Ishigaki)( | A Modular Low Cost Hardware TCP/IP Stack Implementation Adding Direct Network Capabilities to Same On-Chip Embedded Applications Using Xilinx Spartan3 FPGA Nadav Bergstein, Hakaru Tamukoh, Masatoshi Sekine (Tokyo Univ. of Agric and Tech.) CAS2010-128 SIP2010-144 CS2010-98 |
As multi-processor based computers and electronic devices become the norm, a further emphasis is made on achieving task... [more] |
CAS2010-128 SIP2010-144 CS2010-98 pp.155-160 |
| VLD | 2011-03-03 14:10 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | A Circuit Synthesis for Dynamic Reconfigurable Processor Nobuyuki Araki, Takashi Kambe (Kinki Univ.) VLD2010-131 |
Dynamic reconfiguraible processors can implement large-scale and complicated circuits by changing its configurations dur... [more] | VLD2010-131 pp.87-92 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 14:30 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Implementation of Dynamic Reconfigurable Processor with Multi-Accelerator Shuhei Igari, Junji Kitamichi, Yuichi Okuyama, Kenichi Kuroda (Aizu Univ.) VLD2010-108 CPSY2010-63 RECONF2010-77 |
Recently, System on a Chip (SoC) has problems increasing of the scale of circuit and design cost, because SoC contains m... [more] | VLD2010-108 CPSY2010-63 RECONF2010-77 pp.163-168 |
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