| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD, CPSY, CAS | 2017-12-14 15:10 |
Okinawa | Art Hotel Ishigakijima | Proposal of high precision skew adjustment method with an on-chip setup time measurement circuit Naoto Kamba, Masaki Ishii, Masahiro Sasaki (SIT)  CAS2017-84 ICD2017-72 CPSY2017-81 |
In recent years, clock skew which can be tolerated is reduced because the operating speed of integrated circuits increas... [more] | CAS2017-84 ICD2017-72 CPSY2017-81 p.97 |
| VLD | 2013-03-06 13:40 |
Okinawa | Okinawa Seinen Kaikan | A Delay Control Circuit with Channel Length Decomposition and Its Application Yuichi Toyota, Yuki Nakashima, Toru Fujimura, Shigetoshi Nakatake (Univ of Kitakyushu) VLD2012-158 |
In recent years, as the progress of the semiconductor manufacturing, the variations of circuit performance due to device... [more] | VLD2012-158 pp.123-128 |
| CAS | 2008-02-01 09:25 |
Okinawa | A Post-Silicon Clock Tunig Method without Measuring the Variation Effects in Clock Signals Yuko Hashizume, Yasuhiro Takashima (Univ. of Kitakyushu), Yuichi Nakamura (NEC) CAS2007-95 |
In deep-submicron technologies, process variations can significantly affect the performance and yield of VLSI chips. Des... [more] | CAS2007-95 pp.7-12 |
|
| VLD, IPSJ-SLDM | 2007-05-11 10:20 |
Kyoto | Kyodai Kaikan | A Clock Deskew Method using PDE with Discrete Delay Yuko Hashizume, Naoki Otani, Yasuhiro Takashima (Univ. of Kitakyushu), Yuichi Nakamura (NEC) VLD2007-9 |
In deep-submicron technology, process variations can severely affect the performance and the yield of VLSI chips. As a c... [more] | VLD2007-9 pp.13-18 |
| ICD, VLD | 2007-03-08 11:10 |
Okinawa | Mielparque Okinawa | A Clock Deskew Method Using Statisical Presumption Naoki Ootani, Yuko Hashizume, Yasuhiro Takashima (Univ. of Kitayushu), Yuichi Nakamura (NEC) |
In deep-submicron technology, process variations can severely affect the performance and the yield of VLSI chips. As a c... [more] | VLD2006-126 ICD2006-217 pp.43-48 |
| ICD | 2005-05-27 16:10 |
Hyogo | Kobe Univ. | A Programmable On-Chip Picosecond Jitter Measurement Circuit without a Reference Clock Kiyotaka Ichiyama, Masahiro Ishida, Takahiro Yamaguchi (Advantest Labs.), Mani Soma (Univ. of Washington), Masakatsu Suda, Toshiyuki Okayasu, Daisuke Watanabe, Kazuhiro Yamamoto (Advantest) |
A new on-chip jitter measurement circuit, which does not require a reference clock, is proposed. It consists of a combin... [more] | ICD2005-38 pp.57-60 |
[Return to Top Page]