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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, CPSY, RECONF, CPM, ICD, IE
(Joint) [detail]		 2016-11-28
15:30		 Osaka Ritsumeikan University, Osaka Ibaraki Campus Circuit Simulation Method Using Bimodal Defect-Centric Model of Random Telegraph Noise on 40 nm SiON Process
Michitarou Yabuuchi, Azusa Oshima, Takuya Komawaki, Kazutoshi Kobayashi, Ryo Kishida, Jun Furuta (KIT), Pieter Weckx (KUL/IMEC), Ben Kaczer (IMEC), Takashi Matsumoto (Univ. of Tokyo), Hidetoshi Onodera (Kyoto Univ.) VLD2016-52 DC2016-46		 We propose a circuit analysis method using the bimodal RTN (random telegraph
noise) model of the defect-centric distri... [more]		 VLD2016-52 DC2016-46
pp.49-54
SDM 2016-10-27
10:50		 Miyagi Niche, Tohoku Univ. Behavior of Random Telegraph Noise toward Bias Voltage Changing
Takezo Mawaki, Akinobu Teramoto, Rihito Kuroda, Shinya Ichino, Tetsuya Goto, Tomoyuki Suwa, Shigetoshi Sugawa (Tohoku Univ.) SDM2016-75		 As the progression of MOSFETs scaling down continues, the impacts of RTN (Random Telegraph Noise) on the MOSFETs have be... [more] SDM2016-75
pp.35-38
VLD 2011-03-02
17:00		 Okinawa Okinawaken-Danjo-Kyodo-Sankaku Center [Fellow Memorial Lecture] Understanding CMOS Variability for More Moore
Hidetoshi Onodera (Kyoto Univ./JST) VLD2010-124		 With the device dimensions in the nanometer regime,
variability becomes a serious concern in LSI design.
Aggressive sc... [more]		 VLD2010-124
p.49
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