| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICTSSL, CAS | 2018-01-25 15:40 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Design techniques for wireless communication and image processing IP cores Hiroshi Tsutsui (Hokkaido Univ.)  CAS2017-120 ICTSSL2017-47 |
Owing to the advancement of CMOS device downsizing, the capacity of wireless communication and the resolution of various... [more] | CAS2017-120 ICTSSL2017-47 p.55 |
| RECONF | 2014-09-18 14:10 |
Hiroshima | Prototype of fault tolerant FPGA using 65nm CMOS process Motoki Amagasaki, Takuya Kajiwara, Kentaro Fujisawa, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2014-18 |
我々はSoC（System on a Chip）に搭載されるFPGA-IP（Field Programmable Gate Array Intellectual Property）コアに焦点をあてたFT-FPGA（Fault Tolera... [more] |
RECONF2014-18 pp.7-12 |
|
| RECONF | 2014-09-19 13:30 |
Hiroshima | FPGA implementation of a Compact Processor Yukiyama for tiny SoC Yuichi Watanabe, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.) RECONF2014-31 |
This paper proposes a small soft-core processor architecture that can be mapped to a CPLD. This paper describes the det... [more] |
RECONF2014-31 pp.81-86 |
|
| SIS | 2013-06-14 10:00 |
Kagoshima | Houzan Hall (Kagoshima) | [Tutorial Lecture]
Design Case Study of Image Processing Hardware IP
-- Development of Retinex-based Image Enhancement IP Core -- Hiroshi Tsutsui (Hokkaido Univ.) SIS2013-10 |
In recent years, the demand for image processing has been growing steadily with the wide use of digital imaging devices ... [more] | SIS2013-10 pp.47-52 |
| RECONF | 2013-05-21 11:25 |
Kochi | Kochi Prefectural Culture Hall | A defect-robust FPGA-IP core architecture Motoki Amagasaki, Kazuki Inoue, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2013-13 |
In this paper, we propose fault-tolerant FPGA -IP cores for system LSI. Unlike discrete FPGAs, in which the integration... [more] |
RECONF2013-13 pp.67-72 |
| SIP, RCS | 2013-01-31 10:45 |
Hiroshima | Viewport-Kure-Hotel (Kure) | A study on a FPGA implementation of real time foreground segmentation Tomohito Kajimoto, Ryo Yagi, Takao Nishitani (Tokyo Metropolitan Univ.) SIP2012-83 RCS2012-240 |
A prototype processor based on the multi-resolution GMM Foreground Segmentation algorithm by using Walsh Transform domai... [more] | SIP2012-83 RCS2012-240 pp.13-18 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-UBI, IPSJ-MBL [detail] | 2010-03-27 16:00 |
Tokyo | A Topology Decision Approach of IP Cores for Throughput Improvement of Application Specific NoC System Hiroshi Uchikoshi (TUT), Makoto Sugihara (TUT/JST) CPSY2009-88 DC2009-85 |
The continuous effort in shrinking the size of a transistor causes a wire delay to increase relatively faster than a gat... [more] | CPSY2009-88 DC2009-85 pp.321-326 |
|
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-04 10:40 |
Kochi | Kochi City Culture-Plaza | A Proposal of Message Driven IP Core Interface Ryuta Sasaki, Tsugio Nakamura, Hiroshi Kasahara, Narito Fuyutsume (Tokyo Denki Univ.) CPSY2009-48 |
In a ULSI such as SoC, various IP cores developed by different firms are integrated into single-chip. Therefore problems... [more] | CPSY2009-48 pp.31-36 |
| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-29 10:55 |
Kanagawa | A Proposal of Message Driven IP Core Interface Ryuta Sasaki, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara, Teruo Tanaka (Tokyo Denki Univ.) VLD2008-96 CPSY2008-58 RECONF2008-60 |
In a ULSI such as SoC, various IP cores with different development firms are integrated in single-chip. Therefore proble... [more] | VLD2008-96 CPSY2008-58 RECONF2008-60 pp.31-36 |
|
| SIS | 2008-06-13 13:15 |
Hokkaido | An Architecture of Photo Core Transform in HD Photo Coding System for Embedded System of Various Bandwidths Koichi Hattori (Kyoto Univ.), Hiroshi Tsutsui (Osaka Univ.), Hiroyuki Ochi (Kyoto Univ.), Yukihiro Nakamura (Ritsumeikan Univ.) SIS2008-21 |
In this paper, we propose a novel architecture of photo core transform (PCT) which is used as transformation of image da... [more] | SIS2008-21 pp.39-44 |
|
| ICD, SIP, IE, IPSJ-SLDM | 2006-10-26 09:00 |
Miyagi | A Cryptographic Communication Technique between IP cores in ULSI Masafumi Hayakawa (Tokyo Denki Univ.), Tsugio Nakamura (Kokusai junior colleg), Hiroshi Kasahara, Narito Fuyutsume, Teruo Tanaka (Tokyo Denki Univ.) |
The paper proposes a communication method between IP cores, including the standardization on the interface between IP co... [more] | SIP2006-83 ICD2006-109 IE2006-61 pp.1-6 |
|
| ICD, SIP, IE, IPSJ-SLDM | 2006-10-26 16:35 |
Miyagi | A self-support oriented IP core design method Hiroyuki Hatakenaka (TDU), Tsugio Nakamura (Kokusai Junior College), Hiroshi Kasahara, Narito Fuyutsume, Teruo Tanaka (TDU) |
For designing an integrated circuit with the scale of System LSI or SoC, it is reasonable to reuse the circulating IP c... [more] |
SIP2006-98 ICD2006-124 IE2006-76 pp.87-92 |
|
[Return to Top Page]