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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2019-03-17 17:45 |
Kagoshima | Nishinoomote City Hall (Tanega-shima) |  CPSY2018-110 DC2018-92 |
(To be available after the conference date) [more] | CPSY2018-110 DC2018-92 pp.193-198 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-07 09:00 |
Hiroshima | Satellite Campus Hiroshima | A Scalable Multi-Path Selection Method for High-Throughput Interconnection Networks Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) CPSY2018-38 |
(To be available after the conference date) [more] | CPSY2018-38 pp.11-16 |
| CPSY, DC, IPSJ-ARC (Joint) [detail] |
2018-07-31 16:15 |
Kumamoto | Kumamoto City International Center | Measuring and Understanding Throughput of Routing Algorithms Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) CPSY2018-23 |
(To be available after the conference date) [more] | CPSY2018-23 pp.133-138 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-08 09:00 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | CPSY2017-44 |
The number of computing nodes increases for both on-chip multi-core systems and supercomputers. Therefore, the network l... [more] | CPSY2017-44 pp.23-28 |
| CPSY, DC, IPSJ-ARC (Joint) [detail] |
2017-07-27 13:30 |
Akita | Akita Atorion-Building (Akita) | Some Simulation Methods for Large-Scale NoCs Takashi Yokota, Kanemitsu Ootsu, Takeshi Ohkawa (Utsunomiya Univ.) CPSY2017-25 |
(To be available after the conference date) [more] | CPSY2017-25 pp.105-110 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-25 14:50 |
Kanagawa | Hiyoshi Campus, Keio Univ. | Design and Evaluation of A Suboptimal Unidirectional Network Tomohiro Totoki, Hiroshi Nakahara, Daichi Fujiki (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) VLD2016-101 CPSY2016-137 RECONF2016-82 |
(To be available after the conference date) [more] | VLD2016-101 CPSY2016-137 RECONF2016-82 pp.215-220 |
| CPSY, DC, IPSJ-ARC (Joint) [detail] |
2016-08-10 18:00 |
Nagano | Kissei-Bunka-Hall (Matsumoto) | CPSY2016-39 |
(To be available after the conference date) [more] | CPSY2016-39 pp.281-286 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2016-03-25 09:30 |
Nagasaki | Fukue Bunka Hall/Rodou Fukushi Center | Blah Blah Blah Michihiro Koibuchi (NII), Daichi Fujiki (Keio U), Kiyo Ishii (AIST), Ikki Fujiwara (NII), Hiroki Matsutani, Hideharu Amano (Keio U) CPSY2015-147 DC2015-101 |
(To be available after the conference date) [more] | CPSY2015-147 DC2015-101 pp.157-162 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2016-03-25 09:55 |
Nagasaki | Fukue Bunka Hall/Rodou Fukushi Center | An Effective Virtual Channel Allocation Method for Deterministic Deadlock-free Routing Ryuta Kawano, Hiroshi Nakahara (Keio Univ.), Ikki Fujiwara (NII), Hiroki Matsutani, Hideharu Amano (Keio Univ.), Michihiro Koibuchi (NII) CPSY2015-148 DC2015-102 |
Distributed routing methods with small routing tables are scalable design on irregular networks for large-scale High Per... [more] | CPSY2015-148 DC2015-102 pp.163-168 |
| PN | 2016-03-07 17:00 |
Okinawa | Okinawaken Seinenkaikan | [Invited Talk]
Network Technology of Supercomputers Michihiro Koibuchi (NII) PN2015-114 |
(To be available after the conference date) [more] | PN2015-114 pp.63-68 |
| VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] | 2016-01-20 16:10 |
Kanagawa | Hiyoshi Campus, Keio University | An Efficient NoC with Decentralized Routers Ryota Yasudo, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano, Tadao Nakamura (Keio Univ.) VLD2015-95 CPSY2015-127 RECONF2015-77 |
(To be available after the conference date) [more] | VLD2015-95 CPSY2015-127 RECONF2015-77 pp.149-154 |
| ICD, CPSY | 2015-12-18 14:30 |
Kyoto | Kyoto Institute of Technology | A Low Latency Distributed Routing Method for Random Topologies in HPC Networks Ryuta Kawano, Hiroshi Nakahara (Keio Univ.), Ikki Fujiwara (NII), Hiroki Matsutani, Hideharu Amano (Keio Univ.), Michihiro Koibuchi (NII) ICD2015-90 CPSY2015-103 |
End-to-end network latency has become an important issue for parallel application on large-scale High Performance Comput... [more] | ICD2015-90 CPSY2015-103 pp.105-110 |
| CPSY, DC, IPSJ-ARC (Joint) [detail] |
2015-08-04 18:30 |
Oita | B-Con Plaza (Beppu) | Acceleration of Large-scale Interconnection Network Simulator by Using GPU Yuki Suzuki, Takashi Yokota, Kanemitsu Ootsu, Takeshi Ohkawa (Utsunomiya Univ.) CPSY2015-25 |
When the large-scale parallel computing system that uses a lot of computing nodes aims at performance improvement, inter... [more] | CPSY2015-25 pp.97-102 |
| CPSY, DC, IPSJ-ARC (Joint) [detail] |
2015-08-06 10:45 |
Oita | B-Con Plaza (Beppu) | An Improved Algorithm for Random Topology Generation Daisuke Takafuji, Satoshi Fujita, Koji Nakano (Hiroshima Univ.), Ikki Fujiwara, Michihiro Koibuchi (NII) CPSY2015-37 |
(To be available after the conference date) [more] | CPSY2015-37 pp.217-221 |
| CPSY, DC, IPSJ-ARC (Joint) [detail] |
2015-08-06 11:15 |
Oita | B-Con Plaza (Beppu) | Let's Solve the Order/Degree Problem to Make the Lowest-latency Interconnections Ikki Fujiwara (NII), Satoshi Fujita, Koji Nakano (Hiroshima Univ.), Takeru Inoue (NTT), Michihiro Koibuchi (NII) CPSY2015-38 |
(To be available after the conference date) [more] | CPSY2015-38 pp.223-228 |
| RECONF, CPSY, VLD, IPSJ-SLDM [detail] | 2015-01-29 09:35 |
Kanagawa | Hiyoshi Campus, Keio University | Turbo Boost Router: An On-Chip Router Supporting Deterministic and Adaptive Routings Natsuki Homma, Go Matsumura (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano, Hiroki Matsutani (Keio Univ.) VLD2014-116 CPSY2014-125 RECONF2014-49 |
(To be available after the conference date) [more] | VLD2014-116 CPSY2014-125 RECONF2014-49 pp.19-24 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 09:15 |
Oita | B-ConPlaza | Scalable and Low Latency Structure for Castle of Chips Hiroshi Nakahara, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) CPSY2014-79 |
Castle of Chips(CoC) is a chip stacking structure without chip-to-chip wired interconnection. Instead, each chip uses in... [more] | CPSY2014-79 pp.39-44 |
| CPSY, DC (Joint) |
2014-07-29 10:45 |
Niigata | Toki Messe, Niigata | Interconnect Design for Low Latency, High Topological Embeddability and Partitioning Capability by Supplementary Optical Circuit Switches Ryuta Kawano (Keio Univ.), Ikki Fujiwara (NII), Hiroki Matsutani, Hideharu Amano (Keio Univ.), Michihiro Koibuchi (NII) CPSY2014-20 |
This paper focuses on how to efficiently run multiple small parallel applications in a single High-performance computing... [more] | CPSY2014-20 pp.61-66 |
| CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] | 2014-03-16 10:50 |
Okinawa | HPC interconnect for high topological embeddability by supplementary optical circuit switches Ryuta Kawano (Keio Univ.), Ikki Fujiwara (NII), Hiroki Matsutani, Hideharu Amano (Keio Univ.), Michihiro Koibuchi (NII) CPSY2013-111 DC2013-98 |
Our goal is to run multiple parallel applications that have various communication patterns among participating processes... [more] | CPSY2013-111 DC2013-98 pp.253-258 |
|
| DC, CPSY | 2013-04-26 17:05 |
Tokyo | A low latency topology for NoC using multiple host links Ryuta Kawano (Keio Univ.), Ikki Fujiwara (NII), Hiroki Matsutani, Hideharu Amano (Keio Univ.), Michihiro Koibuchi (NII) CPSY2013-9 DC2013-9 |
In recent many-core architectures, the number of cores has been steadily increasing. Therefore, network latency between ... [more] | CPSY2013-9 DC2013-9 pp.49-54 |
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