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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD | 2017-04-20 14:15 |
Tokyo | [Invited Lecture]
TLC NAND Flash Memory Control Techniques to Reduce Errors of Read-Hot and Cold Data for Data Centers Toshiki Nakamura, Atsuro Kobayashi, Ken Takeuchi (Chuo Univ.)  ICD2017-6 |
In cloud data centers, NAND flash memory stores both read-hot and cold data. This paper describes that the threshold vol... [more] | ICD2017-6 pp.29-34 |
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| ICD | 2017-04-20 14:55 |
Tokyo | [Invited Lecture]
First demonstration of FinFET Split-Gate MONOS for High-Speed and Highly-Reliable Embedded Flash in 16/14nm-node and beyond Shibun Tsuda, Yoshiyuki Kawashima, Kenichiro Sonoda, Atsushi Yoshitomi, Tatsuyoshi Mihara, Shunichi Narumi, Masao Inoue, Seiji Muranaka, Takahiro Maruyama, Tomohiro Yamashita, Yasuo Yamaguchi (Renesas Electronics), Digh Hisamoto (Hitachi) ICD2017-7 |
FinFET split-gate metal-oxide nitride oxide silicon (SG-MONOS) Flash memories have been fabricated and operated for the ... [more] | ICD2017-7 pp.35-38 |
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| ICD | 2017-04-20 15:20 |
Tokyo | [Invited Talk]
Embedded Flash Technology for Automotive Applications Masaya Nakano, Takashi Ito, Tadaaki Yamauchi, Yasuo Yamaguchi, Takashi Kono, Hideto Hidaka (Renesas Electronics) ICD2017-8 |
Higher fuel-efficient engine and advanced driver assistance system (ADAS) require the further progress of embedded Flash... [more] | ICD2017-8 pp.39-44 |
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| ICD | 2017-04-20 16:10 |
Tokyo | [Invited Talk]
A 512Gb 3b/Cell Flash Memory on 64-Word-Line-Layer BiCS Technology Ryuji Yamashita, Sagar Magia (WDC), Tsutomu Higuchi, Kazuhide Yoneya, Toshio Yamamura (Toshiba), Hiroyuki Mizukoshi, Shingo Zaitsu, Minoru Yamashita, Shunichi Toyama, Norihiro Kamae, Juan Lee, Shuo Chen, Jiawei Tao, William Mak, Xiaohua Zhang (WDC) ICD2017-9 |
A 512Gb 3b/cell flash has been developed on a 64-WL-layer BiCS technology. By using a four-block-EOC row decoding approa... [more] | ICD2017-9 pp.45-50 |
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| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2017-03-09 15:50 |
Okinawa | Kumejima Island | Near-data processing for genome analysis using software-controlled SSD Kuwamura, Shinya, Kazama, Satoshi, Yoshida, Eiji, Ogawa, Junji, Miyoshi, Takashi, Noguchi, Yasuo (Fujitsu Labs.) CPSY2016-139 DC2016-85 |
Recently, a sort of near-data processing is a hot topic, in order to reduce data transfer cost and get higher system per... [more] | CPSY2016-139 DC2016-85 pp.45-50 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2017-03-10 17:00 |
Okinawa | Kumejima Island | A Scalable Data Centric Converged System for Big Data Analytics Yuki Sasaki, Kenji Takahashi, Keishi Sakanushi, Atsuhiro Kinoshita (Toshiba) CPSY2016-162 DC2016-108 |
Data analytics for IoT market is the most important issue today. Data needs to be converted to relevant information in a... [more] | CPSY2016-162 DC2016-108 pp.399-404 |
| SDM | 2017-01-30 13:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
First Demonstration of FinFET Split-Gate MONOS for High-Speed and Highly-Reliable Embedded Flash in 16/14nm-node and Beyond Shibun Tsuda, Yoshiyuki Kawashima, Kenichiro Sonoda, Atsushi Yoshitomi, Tatsuyoshi Mihara, Shunichi Narumi, Masao Inoue, Seiji Muranaka, Takahiro Maruyama, Tomohiro Yamashita, Yasuo Yamaguchi (Renesas Electronics), Digh Hisamoto (Hitachi) SDM2016-134 |
FinFET split-gate metal-oxide nitride oxide silicon (SG-MONOS) Flash memories have been fabricated and operated for the ... [more] | SDM2016-134 pp.17-20 |
| IT, SIP, RCS | 2017-01-20 10:00 |
Osaka | Osaka City Univ. | A Group Theoretic Approach to Rank-Modulation Rewriting Codes with Multi-cell Ranking and its Applications Takeru Sudo, Tomoharu Shibuya (Sophia Univ) IT2016-86 SIP2016-124 RCS2016-276 |
In this paper, we propose a group theoretic representation suitable for the rank-modulation rewriting codes for flash me... [more] | IT2016-86 SIP2016-124 RCS2016-276 pp.231-236 |
| ICD, CPSY | 2016-12-15 15:30 |
Tokyo | Tokyo Institute of Technology | [Poster Presentation]
Analysis of Read Disturb Error in NAND Flash Memory Hikaru Watanabe, Atsuro Kobayashi, Ken Takeuchi (Chuo Univ.) ICD2016-66 CPSY2016-72 |
Recently, as cloud computing technology and Social Networking Service spread, the applications whose data is read locall... [more] | ICD2016-66 CPSY2016-72 p.51 |
| ICD, CPSY | 2016-12-15 15:30 |
Tokyo | Tokyo Institute of Technology | [Poster Presentation]
Error Pattern Analysis among Scaled Generations of NAND Flash Memories Yukiya Sakaki, Yusuke Yamaga, Ken Takeuchi (Chuo Univ.) ICD2016-69 CPSY2016-75 |
The capacity of NAND flash memory can be expanded by memory cell scaling. However, bit-errors are increased by memory ce... [more] | ICD2016-69 CPSY2016-75 p.57 |
| ICD, CPSY | 2016-12-15 15:30 |
Tokyo | Tokyo Institute of Technology | [Poster Presentation]
Error Analysis of NAND Flash Memories for Long-Term Storage Kyoji Mizoguchi, Tomonori Takahashi, Seiichi Aritome, Ken Takeuchi (Chuo Univ.) ICD2016-72 CPSY2016-78 |
Recently, a digital data on art, culture and history which required data-retention (DR) time from 10 to 100 years or mor... [more] | ICD2016-72 CPSY2016-78 p.63 |
| ICD, CPSY | 2016-12-15 15:30 |
Tokyo | Tokyo Institute of Technology | [Poster Presentation]
A Highly Reliable Method with Data-Retenrion Characteristics in TLC NAND Flash Memories Toshiki Nakamura, Yoshiaki Deguchi, Ken Takeuchi (Chuo Univ.) ICD2016-73 CPSY2016-79 |
The capacity of NAND flash memory can be expanded by multi-level cell technology. In particular, 3-bit/cell triple-level... [more] | ICD2016-73 CPSY2016-79 p.65 |
| ICD, CPSY | 2016-12-15 15:30 |
Tokyo | Tokyo Institute of Technology | [Poster Presentation]
Reduction of Data-Retention Error in TLC NAND Flash Memories Yuichi Sato, Yoshiaki Deguchi, Atsuro Kobayashi, Ken Takeuchi (Chuo Univ.) ICD2016-76 CPSY2016-82 |
The cost of NAND flash memory is reduced by scaling and multi-level cell technologies. However, the reliability of tripl... [more] | ICD2016-76 CPSY2016-82 p.75 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-29 09:25 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Optimal configuration design of SCM and MLC/TLC NAND flash memory in semiconductor storage system Chihiro Matsui, Yusuke Yamaga, Yusuke Sugiyama, Ken Takeuchi (Chuo Univ.) CPM2016-77 ICD2016-38 IE2016-72 |
In order to manage wide variety of data at high speed, a tri-hybrid storage system has been proposed with using storage ... [more] | CPM2016-77 ICD2016-38 IE2016-72 pp.7-10 |
| IT | 2016-07-28 14:55 |
Fukuoka | Seminar House, Fukuoka Univ. | Calculation of Asymptotic Code Rate of Balanced Code with ICI Constraint Hiroshi Kamabe (Gifu Univ) IT2016-26 |
The asymptotic code rate of a constraint satisfying the ICI free and the balance constraints can be drived from a con... [more] |
IT2016-26 pp.31-36 |
| ICD | 2016-04-15 09:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Lecture]
Faster LBA scrambler utilized SSD with Garbage Collection Optimization Chihiro Matsui, Asuka Arakawa, Chao Sun, Tomoko Ogura Iwasaki, Ken Takeuchi (Chuo Univ.) ICD2016-13 |
(To be available after the conference date) [more] | ICD2016-13 pp.65-69 |
| ICD | 2016-04-15 10:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
A 90nm Embedded 1T-MONOS Flash Macro for Automotive Applications with 0.07mJ/8kB Rewrite Energy and Endurance Over 100M Cycles Under Tj of 175°C Satoru Nakanishi, Hidenori Mitani, Ken Matsubara, Hiroshi Yoshida, Takashi Kono, Yasuhiko Taito, Takashi Ito, Takashi Kurafuji, Kenji Noguchi, Hideto Hidaka, Tadaaki Yamauchi (Renesas) ICD2016-15 |
A first-ever 90nm embedded 1T-MONOS Flash macro is presented to realize automotive reliability and simple process integr... [more] | ICD2016-15 pp.77-81 |
| IT, ISEC, WBS | 2016-03-11 11:15 |
Tokyo | The University of Electro-Communications | Construction of WOM codes for multilevel flash memories based of integer programming Yoju Fujino, Tadashi Wadayama (NIT) IT2015-129 ISEC2015-88 WBS2015-112 |
In this paper, we proposed a construction of non-binary WOM (Write-Once-Memory) codes for multilevel ($q$-level) fla... [more] |
IT2015-129 ISEC2015-88 WBS2015-112 pp.169-174 |
| IT, ISEC, WBS | 2016-03-11 11:40 |
Tokyo | The University of Electro-Communications | Asymptotics Zero Error Capacity on Nearest Neighbor Error Channels with Multilevel Alphabet Takafumi Nakano, Tadashi Wadayama (NIT) IT2015-130 ISEC2015-89 WBS2015-113 |
This paper evaluates the zero error capacity of Nearest Neighbor Error channels with multilevel alphabet (NNE channels).... [more] | IT2015-130 ISEC2015-89 WBS2015-113 pp.175-180 |
| DC | 2015-12-18 14:00 |
Niigata | Kurieito Mulakami (Murakami City) | Error Correcting Codes Considering P/E Cycles for NAND Flash Memories Mampei Asai, Masato Kitakami (Chiba Univ.) DC2015-76 |
I Recently, multi-level cell (MLC) NAND flash memory, which has memory cells capable to store 2 or more bits of informat... [more] | DC2015-76 pp.17-22 |
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