IEICE Technical Committee Submission System
Conference Schedule		 Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (Searched in: All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 4 of 4  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
CPSY, DC, IPSJ-ARC
(Joint) [detail]		 2018-07-30
09:30		 Kumamoto Kumamoto City International Center Performance Evaluation of MPI Parallel Program on Android Cluster with Wireless Network
Hiroki Sugiyama, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota (Utsunomiya Univ.) CPSY2018-13		 Recently, many mobile devices including smartphones and table devices employs multi-core processor and GPU and have adva... [more] CPSY2018-13
pp.1-6
ICD, CPSY, CAS 2017-12-14
13:40		 Okinawa Art Hotel Ishigakijima Performance Evaluation of Android Cluster Computer using Open MPI
Hiroki Sugiyama, Masahiro Nissato, Kohta Shigenobu, Kanemitsu Ootsu, Takashi Yokota, Takeshi Ohkawa (Utsunomiya Univ.) CAS2017-72 ICD2017-60 CPSY2017-69		 Recently, many mobile devices including smartphones and table devices employs multi-core processor and GPU and have adva... [more] CAS2017-72 ICD2017-60 CPSY2017-69
pp.45-50
CPSY, DC
(Joint)		 2014-07-30
09:50		 Niigata Toki Messe, Niigata Implementation of Wireless Connected Android Cluster Computer System Supporting Automatic Clustering
Yusuke Arai, Kanemitsu Ootsu, Takashi Yokota, Takeshi Ohkawa (Utsunomiya Univ.) CPSY2014-34		 In recent years, high-performance mobile devices such as smartphones and tablet terminals spread rapidly, and they are b... [more] CPSY2014-34
pp.143-148
RECONF, VLD, CPSY, IPSJ-SLDM [detail] 2011-01-17
12:05		 Kanagawa Keio Univ (Hiyoshi Campus) Parallelization of the channel width search for FPGA routing
Hiroomi Sawada, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto) VLD2010-89 CPSY2010-44 RECONF2010-58		 As the FPGA becomes resourceful, the design time becomes longer.
Especially, routing process occupies the large portion... [more]		 VLD2010-89 CPSY2010-44 RECONF2010-58
pp.31-36
 Results 1 - 4 of 4  /   
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan