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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD | 2011-09-26 14:50 |
Fukushima | University of Aizu | MSA: Mixed Stochastic Algorithm for Placement with Larger Solution Space Yiqiang Sheng (Tokyo Inst. of Tech.), Atsushi Takahashi (Osaka Univ.), Shuichi Ueno (Tokyo Inst. of Tech.)  VLD2011-42 |
The optimization techniques for VLSI/PCB placement with larger solution space and more objectives are facing big challen... [more] | VLD2011-42 pp.11-16 |
| CAS | 2011-01-26 11:20 |
Kumamoto | Kumamoto University | On the Energy-Aware Mapping for NoCs Masayoshi Arai, Satoshi Tayu, Shuichi Ueno (Tokyo Inst. of Tech.) CAS2010-100 |
To overcome the complex communication problems that arise as the number of on-chip components increases, NoCs have been ... [more] | CAS2010-100 pp.87-92 |
| MSS, CAS | 2010-11-18 13:00 |
Osaka | Kansai Univ. | On the Complexity of Three-Dimensional Orthogonal Face Routing Satoshi Tayu, Shuichi Ueno (Tokyo Inst. of Tech.) CAS2010-68 CST2010-41 |
The 3-D switchbox routing is a fundamental problem on the physical design of 3-D integrated circuits. The 3-D channel is... [more] | CAS2010-68 CST2010-41 pp.19-24 |
| MSS, CAS | 2009-11-27 13:25 |
Aichi | Nagoya University | Universal Test Sets for Reversible Circuits Satoshi Tayu, Shota Fukuyama, Shuichi Ueno (Tokyo Inst. of Tech.) CAS2009-55 CST2009-28 |
A set of test vectors is complete for a reversible circuit if it covers all stuck-at faults on the wires of the circuit.... [more] | CAS2009-55 CST2009-28 pp.59-64 |
| CAS, CS, SIP | 2009-03-03 13:10 |
Gifu | Nagaragawa Convention Center | [Poster Presentation]
A Note on Two Problems of Nano-PLA Design Anish Man Singh Shrestha, Tomoki Yamada, Satoshi Tayu, Shuichi Ueno (Tokyo Inst of Tech) CAS2008-133 SIP2008-196 CS2008-107 |
This paper shows that the subgraph isomorphism problem is NP-hard even for bipartite permutation graphs, while the balan... [more] | CAS2008-133 SIP2008-196 CS2008-107 pp.183-184 |
| CAS, MSS | 2008-11-06 09:30 |
Osaka | Osaka University | On the Three-Dimensional Single-Active-Layer Routing Satoshi Tayu, Shuichi Ueno (Tokyo Inst. of Tech) CAS2008-45 CST2008-23 |
[more] | CAS2008-45 CST2008-23 pp.1-4 |
| CAS, MSS | 2008-11-06 09:55 |
Osaka | Osaka University | Orthogonal Ray Graphs and Nano-PLA Design Anish Man Singh Shrestha, Satoshi Tayu, Shuichi Ueno (Tokyo Inst. of Tech) CAS2008-46 CST2008-24 |
The logic mapping problem and the problem of finding a largest square sub-crossbar with no defects in a defective nano-c... [more] | CAS2008-46 CST2008-24 pp.5-10 |
| CS, SIP, CAS | 2008-03-07 13:00 |
Yamaguchi | Yamaguchi University | [Poster Presentation]
On the Three-Dimensional Orthogonal Drawing of Outerplanar Graphs (Extended Abstract) Takuya Oshima, Satoshi Tayu, Shuichi Ueno (Tokyo Inst. of Tech.) CAS2007-143 SIP2007-218 CS2007-108 |
It has been known that every series-parallel 6-graph has a 2-bend 3-D orthogonal drawing, while it has been open whether... [more] | CAS2007-143 SIP2007-218 CS2007-108 pp.93-94 |
| CS, SIP, CAS | 2008-03-07 13:00 |
Yamaguchi | Yamaguchi University | [Poster Presentation]
An Efficient Quantum Addition Circuit (Extended Abstract) Yoshinori Kawata, Satoshi Tayu, Shuichi Ueno (Tokyo Inst. of Tech.) CAS2007-144 SIP2007-219 CS2007-109 |
We present an efficient addition circuit, using both ripple-carry and carry-lookahead. Our quantum adder accepts two $n$... [more] | CAS2007-144 SIP2007-219 CS2007-109 pp.95-96 |
| CS, SIP, CAS | 2008-03-07 13:00 |
Yamaguchi | Yamaguchi University | [Poster Presentation]
On Orthogonal Ray Graphs with Applications to NanoPLA Design (Extended Abstract) Yohei Kobayashi, Anish Man Singh Shrestha, Satoshi Tayu, Shuichi Ueno (Tokyo Inst. of Tech.) CAS2007-145 SIP2007-220 CS2007-110 |
Motivated by defect tolerance schemes for nanotechnology circuits, the orthogonal ray graphs, a new class of intersecti... [more] |
CAS2007-145 SIP2007-220 CS2007-110 pp.97-98 |
| MSS, CAS | 2007-11-29 14:55 |
Niigata | Niigata University | On the Permutation Routing in All-Optical Caterpillar Networks Anish Man Singh Shrestha, Satoshi Tayu, Shuichi Ueno (Tokyo Inst. of Tech.) CAS2007-71 CST2007-22 |
We consider the optical routing for permutation requests in a WDM all-optical tree network. We show that the optical rou... [more] | CAS2007-71 CST2007-22 pp.23-27 |
| MSS, CAS | 2007-11-30 11:00 |
Niigata | Niigata University | [Fellow Memorial Lecture]
Study of the Graph Theory with Applications to Circuits and Systems Shuichi Ueno (TIT) CAS2007-76 CST2007-27 |
The author has been engaged in research with a number of co-researchers on the graph theory with applications to electri... [more] | CAS2007-76 CST2007-27 p.19 |
| ICD | 2007-04-12 10:00 |
Oita | A high-density 1T-4MTJ MRAM with Self-Reference Sensing Scheme Yasumitsu Murai, Hiroaki Tanizaki (Renesas Design), Takaharu Tsuji, Jun Otani, Yuichiro Yamaguchi, Haruo Furuta, Shuichi Ueno, Tsukasa Oishi, Masanori Hayashikoshi, Hideto Hidaka (Renesas) ICD2007-3 |
A high-density memory cell named 1-Transistor 4-Magnetic Tunnel Junction (1T-4MTJ) has been proposed for Magnetic Random... [more] | ICD2007-3 pp.13-16 |
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| CAS, MSS | 2006-11-21 14:20 |
Nagasaki | Nagasaki Univ. | The Complexity of Three-Dimensional Channel Routing Satoshi Tayu, Shuichi Ueno (Tokyo Inst. of Tech.) |
[more] | CAS2006-61 CST2006-37 pp.37-41 |
| ICD | 2006-04-13 16:40 |
Oita | Oita University | [Panel Discussion]
What is your urgent task in R/D of new embedded memories? Hideto Hidaka (Renesas), Masao Taguchi (SPANSION), Takayuki Kawahara (Hitachi), Daisaburo Takashima (Toshiba), Shuichi Ueno (Renesas), Masashi Takata (Kanazawa Univ.), Masafumi Takahashi (Toshiba) |
Recent advent of emerging memory devices circa 2000 has seen discussions directed mainly to stand-alone memory applicati... [more] | ICD2006-9 p.49 |
| ICD | 2006-04-14 10:25 |
Oita | Oita University | [Special Invited Talk]
Spin-Transfer Torque Writing Technology (STT-RAM) For Future MRAM Hide Nagai, Yiming Huai (Grandis), Shuichi Ueno, Tsuyoshi Koga (Renesas Technology) |
[more] | ICD2006-14 pp.75-80 |
| CAS | 2006-01-11 14:25 |
Miyazaki | On the Three-Dimensional Orthogonal Drawing of Series-Parallel Graphs Satoshi Tayu, Kumiko Nomura, Shuichi Ueno (Tokyo Inst. of Tech.) |
It has been known that every $6$-graph has a $3$-bend $3$-D orthogonal drawing, while it has been open whether every... [more] |
CAS2005-71 pp.7-12 |
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| MSS, CAS | 2005-11-10 11:20 |
Yamaguchi | Yamaguchi University | On the Complexity of Fault Testing for Reversible Circuits Shigeru Ito, Yusuke Ito, Satoshi Tayu, Shuichi Ueno (Tokyo Inst. of Tech.) |
This paper shows that it is NP-hard to generate a minimum complete test set for stuck-at faults on a set of wires of a r... [more] | CAS2005-51 CST2005-20 pp.13-16 |
| MSS, CAS | 2005-11-10 15:50 |
Yamaguchi | Yamaguchi University | On the Two-Dimensional Orthogonal Drawing of Series-Parallel Graphs Satoshi Tayu, Kumiko Nomura, Shuichi Ueno (Tokyo Inst. of Tech.) |
It has been known that every planar $4$-graph has a $2$-bend $2$-D orthogonal drawing with the only exception of octahed... [more] | CAS2005-58 CST2005-27 pp.51-56 |
| ICD | 2005-04-15 10:30 |
Fukuoka | A 1.2V 1Mbit Embedded MRAM Core with Folded Bit-Line Array Architecture Takaharu Tsuji (Renesas Technorogy), Hiroaki Tanizaki (Renesas Device Design), Masatoshi Ishikawa, Jun Otani, Yuichiro Yamaguchi, Shuichi Ueno, Tsukasa Oishi, Hideto Hidaka (Renesas Technorogy) |
A 1Mbit MRAM with a 0.81um2 1-Transistor 1-Magnetic Tunnel Junction (1T-1MTJ) cell using 0.13um 4LM logic technology has... [more] | ICD2005-13 pp.1-6 |
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