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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| PRMU, IBISML, IPSJ-CVIM | 2024-03-04 11:10 |
Hiroshima | Hiroshima Univ. Higashi-Hiroshima campus (Primary: On-site, Secondary: Online) |
Towards Client-aware Clustering Federated Learning based on Representations of Local Models Tatsuya Kaneko, Shinya Takamaeda-Yamazaki (Tokyo Univ.)  IBISML2023-49 |
In the current era of rapidly expanding machine learning, there has been growing concerns and awareness of data privacy ... [more] | IBISML2023-49 pp.65-70 |
| RECONF | 2019-05-10 14:20 |
Tokyo | Tokyo Tech Front | RECONF2019-18 |
(To be available after the conference date) [more] | RECONF2019-18 pp.97-102 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 14:35 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Performance Evaluation of K-best Viterbi Decoder for IoT Applications Thi Hong Tran (NAIST), Dwi Rahma Ariyani, Lina Alfaridah ZH (Andalas Univ.), Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima (NAIST) CPSY2015-70 |
[more] | CPSY2015-70 pp.51-56 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 10:05 |
Oita | B-ConPlaza | Implementation and Evaluation of An Accelerator based on Manymemory Network Ryo Shimizu, Masakazu Tanomoto, Shinya Takamaeda-Yamazaki, Jun Yao, Yasuhiko Nakashima (NAIST) CPSY2014-81 |
In this research, we focus on the data parallelization of stencil computations on a previously proposed memory-network b... [more] | CPSY2014-81 pp.51-56 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 10:30 |
Oita | B-ConPlaza | Convolutional Neural Network Processing on An Accelerator based on Manymemory Network Masakazu Tanomoto, Shinya Takamaeda-Yamazaki, Jun Yao, Yasuhiko Nakashima (NAIST) CPSY2014-82 |
Recently, Convolutional Neural Network (CNN) is widely used for image recognition. GPU is generally preferred to acceler... [more] | CPSY2014-82 pp.57-62 |
| CPSY, DC (Joint) |
2014-07-28 13:15 |
Niigata | Toki Messe, Niigata | An FPGA-based Graph Processing Accelerator with PyCoRAM Shinya Takamaeda-Yamazaki, Tadahiro Edamoto, Jun Yao, Yasuhiko Nakashima (NAIST) CPSY2014-10 |
In order to improve the programmablity of FPGA-based accelerators with higher performance, we are developing PyCoRAM tha... [more] | CPSY2014-10 pp.1-6 |
| CPSY, DC (Joint) |
2014-07-30 09:25 |
Niigata | Toki Messe, Niigata | Instruction Execution Method towards Error Reduction of Neural Network Processing Kazuma Koike, Shinya Takamaeda-Yamazaki, Jun Yao, Yasuhiko Nakashima (NAIST) CPSY2014-33 |
Approximate Computing has attracted attention as a method for reducing power consumption in varies applications, such as... [more] | CPSY2014-33 pp.137-142 |
| RECONF | 2013-09-19 14:15 |
Ishikawa | Japan Advanced Institute of Science and Technology | Development of Memory Management Framework for FPGA-based Prototyping Shinya Takamaeda-Yamazaki (Tokyo Inst. of Tech./JSPS Research Fellow), Kenji Kise (Tokyo Inst. of Tech.) RECONF2013-35 |
FPGA-based rapid prototyping supports faster emulation, but it requires the detailed implementation for each FPGA charac... [more] | RECONF2013-35 pp.91-96 |
| CPSY, VLD, RECONF, IPSJ-SLDM [detail] | 2013-01-17 15:15 |
Kanagawa | Design and Implementation of High Performance Stencil Computer by using Mesh Connected FPGA Arrays Ryohei Kobayashi, Shinya Takamaeda-Yamazaki, Kenji Kise (Tokyo Tech) VLD2012-134 CPSY2012-83 RECONF2012-88 |
We develop an effective stencil computation accelerator by using multiple FPGAs, which employs 2D-mesh architecture conn... [more] | VLD2012-134 CPSY2012-83 RECONF2012-88 pp.159-164 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 09:25 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | Rethinking virtual channel usage in network-on-chip Ryosuke Sasakawa, Naoki Fujieda, Shinya Takamaeda-Yamazaki, Kenji Kise (Tokyo Tech) CPSY2012-51 |
An important requirement of routing algorithm is the freedom from deadlock in Network-on-Chip (NoC).For generating deadl... [more] | CPSY2012-51 pp.21-26 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 09:50 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | Network Performance of Multifunction On-chip Router Architectures Shinya Takamaeda-Yamazaki, Naoki Fujieda, Kenji Kise (Tokyo Inst. of Tech.) CPSY2012-52 |
In order to improve the chip-level dependability, we have proposed SmartCore system, NoC-based DMR (Dual Modular Redunda... [more] | CPSY2012-52 pp.27-32 |
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