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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC | 2016-02-17 10:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation Fuqiang Li, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara (Kyutech)  DC2015-87 |
Both logic paths and clock paths are subject to the impact of IR-Drop which occurs in capture mode during scan test. Thi... [more] | DC2015-87 pp.7-12 |
| DC | 2015-12-18 13:20 |
Niigata | Kurieito Mulakami (Murakami City) | On Measurement of On-Chip Temperature And Voltage Variation Using A Digital Monitor Yousuke Miyake, Takaaki Kato, Takuya Itonaga, Yasuo Sato, Seiji Kajihara (KIT) DC2015-74 |
A digital monitor for measuring a temperature and a voltage of VLSIs is proposed. The monitor can derive measurement res... [more] | DC2015-74 pp.5-10 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-01 15:45 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | [Fellow Memorial Lecture]
Improving System Dependability by VLSI Test Technology Seiji Kajihara (KIT) VLD2015-44 CPM2015-128 ICD2015-53 CPSY2015-64 DC2015-40 RECONF2015-51 |
VLSI Test technology for detection of manufacturing faults has been developed to improve test quality that is the capabi... [more] | VLD2015-44 CPM2015-128 ICD2015-53 CPSY2015-64 DC2015-40 RECONF2015-51 pp.43-44(VLD), pp.9-10(CPM), pp.9-10(ICD), pp.19-20(CPSY), pp.43-44(DC), pp.19-20(RECONF) |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 10:50 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | On Correction of Temperature Influence to Delay Measurement in FPGAs Takeru Kina, Yousuke Miyake, Yasuo Sato, Seiji Kajihara (KIT) VLD2015-63 DC2015-59 |
As a means for delay testing for VLSIs in field, a measurement method of a path delay for a logic circuit using variable... [more] | VLD2015-63 DC2015-59 pp.165-170 |
| DC | 2015-06-16 15:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Method to Identify High Test Power Areas in Layout Design Kohei Miyase (Kyutech), Matthias Sauer, Bernd Becker (Univ. Freiburg), Xiaoqing Wen, Seiji Kajihara (Kyutech) DC2015-18 |
The problems related to power consumption during at-speed testing is becoming more serious. Particularly, excessive peak... [more] | DC2015-18 pp.13-18 |
| DC | 2014-12-19 13:00 |
Toyama | Study on reduction and control of NBTI-induced degradation in FPGA-based ring oscillators Yasuo Sato, Yousuke Miyake, Seiji Kajihara (Kyutech) DC2014-67 |
Ring oscillators are used for variety of applications to enhance reliability on LSIs or FPGAs; however, the performance ... [more] | DC2014-67 pp.1-6 |
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| DC | 2014-12-19 13:25 |
Toyama | A Temperature Monitor Using Ring-Oscillators on FPGA Yousuke Miyake, Yasuo Sato, Seiji Kajihara (kyutech) DC2014-68 |
On-chip temperature monitors are often used to guarantee the reliability of VLSIs and monitors using ring oscillators ha... [more] | DC2014-68 pp.7-12 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 14:45 |
Oita | B-ConPlaza | On-chip delay measurement for FPGAs Kentaro Abe, Yousuke Miyake, Seiji Kajihara, Yasuo Sato (KIT) VLD2014-109 DC2014-63 |
This paper describes an on-chip delay measurement method that targets a logic circuit on an FPGA. While advances in semi... [more] | VLD2014-109 DC2014-63 pp.245-250 |
| DC | 2014-06-20 14:05 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A X-Filling Method for Low-Capture-Power Scan Test Generation Fuqiang Li, Xiaoqing Wen, Kohei Miyase, Stefan Holst, Seiji Kajihara (Kyushu Inst. of Tech.) DC2014-12 |
In order to generate a low capture power test pattern, we propose an X-filling method to suppress local switching activ... [more] |
DC2014-12 pp.15-20 |
| DC | 2014-06-20 14:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Capture Power Evaluation for A Low Power BIST Method Using A TEG Chip Toshiya Nishida (Kyushu Inst. of Tech.), Senling Wang (Ehime Univ.), Yasuo Sato, Seiji Kajihara (Kyushu Inst. of Tech.) DC2014-13 |
Voltage drop by a momentary current change during capture cycles in scan-based testing brings an increase in path delay ... [more] | DC2014-13 pp.21-26 |
| DC | 2013-12-13 13:25 |
Ishikawa | Variable Test-Timing Generation for Built-In Self-Test on FPGA Yasuo Sato, Munehiro Matsuura, Hitoshi Arakawa, Yousuke Miyake, Seiji Kajihara (Kyushu Inst. of Tech.) DC2013-69 |
This paper proposes a variable test-timing generation method that should be used for built-in self-test on FPGA. Applica... [more] | DC2013-69 pp.7-12 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 13:45 |
Kagoshima | A Study on Design Structure of Ring Oscillators with Plural Frequency Characteristics in FPGAs Yousuke Miyake, Masafumi Monden, Yasuo Sato, Seiji Kajihara (Kyusyu Inst. of Tech.) VLD2013-84 DC2013-50 |
FPGAs are used in various embedded systems including highly reliable systems, therefore, it is important to ensure its r... [more] | VLD2013-84 DC2013-50 pp.165-170 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-29 08:30 |
Kagoshima | A Study of Burn-In Test Prediction by Data Mining Satoshi Nonoyama, Yasuo Sato, Seiji Kajihara (Kyushu Inst. of Tech.), Yoshiyuki Nakamura (Renesas Electronics) VLD2013-91 DC2013-57 |
[more] | VLD2013-91 DC2013-57 pp.221-226 |
|
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-29 09:20 |
Kagoshima | Design and evaluation of circuits to control scan-in power in logic BIST Takaaki Kato, Takeru Kina, Yousuke Miyake, Yasuo Sato, Seiji Kajihara (Kyushu Inst. of Tech.) VLD2013-93 DC2013-59 |
Power reduction during Logic BIST is a crucial problem; however, power controlling technologies are required as well as ... [more] | VLD2013-93 DC2013-59 pp.233-238 |
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| DC | 2013-06-21 14:45 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A theretical discussion for testabilty of a degraded LSI in field Yasuo Sato, Seiji Kajihara (Kyushu Inst. of Tech.) DC2013-12 |
Various electronic systems that consist of variety of LSIs require very high reliability in field. However, physical deg... [more] | DC2013-12 pp.13-18 |
| DC | 2013-02-13 16:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Temperature and voltage estimation considering manufacturing variability for a monitoring circuit Yousuke Miyake, Wataru Tsumori, Yasuo Sato, Seiji Kajihara (Kyushu Inst. of Tech.), Yukiya Miura (Tokyo Metropolitan Univ.) DC2012-89 |
Delay increase due to aging phenomena is a critical issue of VLSIs. For detecting such increase in field, a highly accur... [more] | DC2012-89 pp.55-60 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-26 13:00 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | [Invited Talk]
High Field Reliability Using Built-In Self Test Seiji Kajihara (Kyutech) VLD2012-65 DC2012-31 |
On-line test based on delay measurement at power-on/off time or at system idle time of a system allows us to detect dela... [more] | VLD2012-65 DC2012-31 pp.37-42 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-28 14:30 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | Design of temperature and voltage monitoring circuit structure for field test Wataru Tsumori, Yousuke Miyake, Yasuo Sato, Seiji Kajihara (KIT), Yukiya Miura (TMU) VLD2012-101 DC2012-67 |
For improving reliability of LSIs, the delay increase caused by aging during system operation should be detected before ... [more] | VLD2012-101 DC2012-67 pp.243-248 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-28 14:55 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | A Scan-Out Power Reduction Method for Multi-Cycle BIST Senling Wang, Yasuo Sato, Seiji Kajihara, Kohei Miyase (Kyutech) VLD2012-102 DC2012-68 |
Excessive power dissipation in logic BIST is a serious problem. Although many low power BIST approaches that focus on sc... [more] | VLD2012-102 DC2012-68 pp.249-254 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-28 16:00 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | A Method to Estimate the Number of Don't-Care Bits with Netlist Kohei Miyase, Seiji Kajihara, Xiaoqing Wen (KIT) VLD2012-104 DC2012-70 |
X-filling is often utilized so as to achieve test compression, test power reduction, or test quality improvement etc. i... [more] |
VLD2012-104 DC2012-70 pp.261-266 |
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