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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| MSS | 2015-03-06 13:55 |
Ishikawa | IT Business Plaza Musashi | The symbolic model checking by the model extraction from embedded assembly program Tomonori Kato, Ryosuke Konoshita, Kohei Sakurai, Satoshi Yamane (Kanazawa Univ.)  MSS2014-102 |
Embedded systems have been widely used. In addition, embedded systems have been gradually complicated.It is important to... [more] | MSS2014-102 pp.65-70 |
| CAS, SIP, MSS, VLD, SIS [detail] | 2014-07-10 15:40 |
Hokkaido | Hokkaido University | [Panel Discussion]
Management of Technical Committees for Promoting Innovation Kunihiko Hiraishi (JAIST), Takafumi Yamaji (Toshiba), Shigetoshi Nakatake (Univ. of Kitakyushu), Yoshinobu Kajikawa (Kansai Univ.), Satoshi Yamane (Kanazawa Univ.) CAS2014-32 VLD2014-41 SIP2014-53 MSS2014-32 SIS2014-32 |
The four technical committees of System and Signal Processing Subsociety have been holding joint workshop since 2010. We... [more] | CAS2014-32 VLD2014-41 SIP2014-53 MSS2014-32 SIS2014-32 p.169 |
| SS, MSS | 2014-01-31 09:30 |
Aichi | Distributed Online Decison Tree Learning for Stream Data Based on Actor Model Koichi Yamamoto, Kohei Sakurai, Satoshi Yamane (Kanazawa Univ.) MSS2013-61 SS2013-58 |
Because the conventional decision tree learning algorithm is not designed for the large-scale data computing, it isn't p... [more] | MSS2013-61 SS2013-58 pp.59-64 |
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| SS, MSS | 2014-01-31 09:55 |
Aichi | Bounded model checking based in SMT for CISC embedded assembly programs Atsushi Takeshita, Junpei Kobashi, Satoshi Yamane (Kanazawa Univ.) MSS2013-62 SS2013-59 |
In this paper,we describe the method of verification by bounded model checking based in SMT using Code Block for embedde... [more] | MSS2013-62 SS2013-59 pp.65-70 |
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| MSS, CAS, IPSJ-AL [detail] | 2013-11-06 14:00 |
Iwate | Development of specification language for dynamic embedded systems Satoshi Yamane, Makoto Sakai (Kanazawa Univ.) CAS2013-58 MSS2013-37 |
Embedded systems input signals from external environments, and tasks communicate with other tasks, also tasks behave c... [more] |
CAS2013-58 MSS2013-37 pp.23-28 |
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| SS, IPSJ-SE | 2013-10-24 10:30 |
Ishikawa | Symbolic Model Checking of Embedded CISC Assembly Program Kenta Watanabe, Hyejin Jang, Kohei Sakurai, Satoshi Yamane (Kanazawa Univ.) SS2013-36 |
The more complicated embedded systems are, the more difficult verification of safety and reliability is. Therefore, the... [more] |
SS2013-36 pp.1-5 |
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| SS, IPSJ-SE | 2013-10-24 10:50 |
Ishikawa | Development of the Behavior Extractor for Assembly Program of Embedded CISC Microcomputer and Adapting to Model Checking
-- Generating the Model Automatically by Simulation -- Ryosuke Konoshita, Satoshi Yamane, Kohei Sakurai (Kanazawa Univ.) SS2013-37 |
We aim at Model Checking for Embedded Systems. We describe the outline of Behavior Extractor that automatically construc... [more] | SS2013-37 pp.7-12 |
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| SRW | 2013-10-21 11:10 |
Kanagawa | NICT@YRP | Baseline wander compensation method for wireless transmitter baseband Kohji Takano, Yasuteru Kohda, Nobuyuki Ohba, Daiju Nakano, Satoshi Yamane, Yasunao Katayama (IBM Japan) SRW2013-32 |
With the advance of wireless technologies, a wide variety of RF chips and digital baseband logic chips are developed by ... [more] | SRW2013-32 pp.25-30 |
| SIP, CAS, MSS, VLD | 2013-07-11 16:10 |
Kumamoto | Kumamoto Univ. | [Panel Discussion]
Future Outlooks in System and Signal Processing Subsociety
-- A Plan to Develop the Human Resource -- Mitsunori Makino (Chuo Univ.), Keisuke Nakano (Niigata Univ.), Makoto Ikeda (Univ. of Tokyo), Hiroshi Sawada (NTT), Yuichi Nakamura (NEC), Satoshi Yamane (Kanazawa Univ.) CAS2013-13 VLD2013-23 SIP2013-43 MSS2013-13 |
The four technical committees of System and Signal Processing Subsociety have been holding joint workshop since 2010. W... [more] | CAS2013-13 VLD2013-23 SIP2013-43 MSS2013-13 p.69 |
| SRW | 2013-04-19 11:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | FPGA platform with coherent detection for mmwave link experiment Yasuteru Kohda, Nobuyuki Ohba, Daiju Nakano, Kohji Takano, Satoshi Yamane, Yasunao Katayama (IBM Japan) SRW2013-4 |
There has been considerable works on millimeter wave communication technology and this research area is getting hotter r... [more] | SRW2013-4 pp.15-20 |
| KBSE | 2012-11-22 11:25 |
Ishikawa | Kanazawa University | SMT-based Bounded Model Checking for Assembly program Junpei Kobashi, Atsushi Takeshita, Satoshi Yamane (Kanazawa Univ.) KBSE2012-41 |
In this paper, we state property verification by Bounded Model Checking using SMT solver for register level model of ass... [more] | KBSE2012-41 pp.19-24 |
| VLD, CAS, MSS, SIP | 2012-07-02 13:00 |
Kyoto | Kyoto Research Park | Verification of embedded software in Assembly code by SMT prover Atsushi Takeshita, Junpei Kobashi, Satoshi Yamane (Kanazawa Univ.) CAS2012-7 VLD2012-17 SIP2012-39 MSS2012-7 |
We propose the technique of Bounded Model Checking(BMC) for embedded assembly program. We use SMT solver for BMC. We als... [more] | CAS2012-7 VLD2012-17 SIP2012-39 MSS2012-7 pp.37-42 |
| COMP | 2011-04-22 15:15 |
Kyoto | Kyoto University | Computation of quantifier elimination of linear inequlities of first order predicate logic Yuuki Ono, Satoshi Yamane (Kanazawa Univ.) COMP2011-8 |
In this paper, the algorhithm of quantifier elimination of first-order predicate logic for linear inequalities will be d... [more] | COMP2011-8 pp.55-59 |
| MSS | 2010-08-02 14:00 |
Ishikawa | Development Simulator of Dynamic Reconfigurable Processor Chen Shen, Yuki Nakai, Satoshi Yamane (Kanazawa Univ.) CST2010-32 |
[more] | CST2010-32 pp.1-6 |
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| KBSE, SS | 2010-05-28 13:45 |
Kyoto | Doshisha University, Imadegawa Campus | Dynamic Real Time CEGAR Makoto Sakai, Yuji Tanaka, Satoshi Yamane (Kanazawa Univ.) SS2010-12 KBSE2010-12 |
In the present study, it proposes an effective model checking technique to the real time system into which the compositi... [more] | SS2010-12 KBSE2010-12 pp.69-74 |
| KBSE, SS | 2010-05-28 14:25 |
Kyoto | Doshisha University, Imadegawa Campus | Symbolic Verification Method of Priced Probabilistic Timed Automaton with Spaces Katsuya Hatanaka, Hiroshi Kamazawa, Satoshi Yamane (Kanazawa Univ.) SS2010-13 KBSE2010-13 |
Recently, wireless sensor networks attracts attention in various fields. Moreover, with the making of the embedded syste... [more] | SS2010-13 KBSE2010-13 pp.75-79 |
| KBSE, SS | 2010-05-28 15:20 |
Kyoto | Doshisha University, Imadegawa Campus | Implementation and Evaluation of Probabilistic Timed Real-Example Guided Abstraction Refinement Takaya Shimizu, Masaki Takahashi, Satoshi Yamane (Kanazawa Univ.) SS2010-14 KBSE2010-14 |
Probabilistic Timed REGAR (Real-Example Guided Abstraction Refinement) is a subclass of PTCTL(Probabilistic Timed Comput... [more] | SS2010-14 KBSE2010-14 pp.81-86 |
| MSS, CAS | 2009-11-27 09:30 |
Aichi | Nagoya University | Model and Model Checking of Embedded Systems using Probablistic Game Theory Shouta Koshida, Satoshi Yamane (Kanazawa Univ.) CAS2009-51 CST2009-24 |
[more] | CAS2009-51 CST2009-24 pp.35-40 |
| MSS, CAS | 2009-11-27 09:55 |
Aichi | Nagoya University | Model Checking of subclass of PTCTL by Probabilistic Timed REGAR Masaki Takahashi, Atsushi Morishita, Satoshi Yamane (Kanazawa Univ) CAS2009-52 CST2009-25 |
[more] | CAS2009-52 CST2009-25 pp.41-46 |
| MSS | 2009-06-03 14:00 |
Osaka | Setsunan University, Osaka Center | Proposal of Priced probabilistic Timed Automaton with concept of Space, and its Application to Sensor Netwrok Hiroshi Kamazawa, Satoshi Yamane (Kanazawa Univ.) CST2009-2 |
Recently,wireless sensor networks attract attention in various fields. However,as the spatiality such as the range of th... [more] | CST2009-2 pp.7-12 |
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