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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| EE, CPM | 2015-02-27 13:50 |
Tokyo | NTT Musashino R&D Center | Energy Management System Simulation with NetLogo Tomonobu Itagaki, Noboru Ishihara, Takashi Suganuma, Toyonari Shimakage (TIT), Taku Ishibashi, Norikazu Takeuchi (NTT Facilities), Nobuhiko Yamashita (NTT), Kenji Yokoyama, Kazuya Masu (TIT)  EE2014-47 CPM2014-161 |
In the study of large-scale energy management system, NetLogo, an agent-based modeling environment for simulating social... [more] | EE2014-47 CPM2014-161 pp.37-42 |
| EE, CPM | 2015-02-27 14:15 |
Tokyo | NTT Musashino R&D Center | Modeling and Simulation of Home Nanogrid Energy Management System using the internal price of electricity Takashi Suganuma, Noboru Ishihara, Tomonobu Itagaki, Toyonari Shimakage (TIT), Taku Ishibashi, Norikazu Takeuchi (NTT Facilities), Nobuhiko Yamashita (NTT), Kenji Yokoyama, Kazuya Masu (TIT) EE2014-48 CPM2014-162 |
Abstract The prevalence and diffusion of the distributed generator and battery accelerate the autonomous-decentralizing ... [more] | EE2014-48 CPM2014-162 pp.43-48 |
| MW (2nd) |
2014-11-26 - 2014-11-28 |
Overseas | King Mongkut's Institute of Technology Ladkrabang (KMITL), Bangkok | A 0.5-V 5.8-GHz Current-Reuse-VCO-Based PLL with Amplitude Regulation Technique Sho Ikeda, Sang_yeop Lee, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu (Tokyo Tech.) |
This paper presents design and detail measurement results of the ultra-low-power 5.8-GHz PLL with a current-reuse VCO an... [more] | |
| MW | 2013-03-08 13:30 |
Hiroshima | Hiroshima Univ. | [Invited Talk]
A Study of Ultra-Low-Power RF CMOS Transceiver Circuit Technologies Hiroyuki Ito, Sang-Yeop Lee, Sho Ikeda, Jiang Hao, Noboru Ishihara, Kazuya Masu (Tokyo Inst. of Tech.) MW2012-187 |
[more] | MW2012-187 pp.153-156 |
| ICD | 2011-12-15 10:30 |
Osaka | An Inductorless Phase-Locked Loop with Pulse Injection Locking Technique in 90 nm CMOS Sang-Yeop Lee, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu (Tokyo Inst. of Tech.) ICD2011-100 |
An inductorless phase-locked loop with subharmonic pulse injection locking was realized (PLL area: 0.08 $\mathrm{mm}^2$)... [more] | ICD2011-100 pp.1-6 |
|
| EMCJ, ITE-BCT | 2010-03-12 15:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Design and Fabrication of On-chip Integrated Magnetic Field Probe using Low Noise Amplifier Shiori Namba, Wataru Kodate, Masahiro Yamaguchi (Tohoku Univ.), Shoji Kawahito (Shizuoka Univ.), Noboru Ishihara (Tokyo Inst. of Tech.) EMCJ2009-132 |
An on-chip integrated magnetic field probe has been designed and fabricated using CMOS technology. This probe will be us... [more] | EMCJ2009-132 pp.37-42 |
| SR | 2009-07-30 16:20 |
Tokyo | Tokyo institute of technology | [Invited Talk]
RF CMOS Integrated Circuit
-- Reconfigurability and Scalability -- Kazuya Masu, Noboru Ishihara, Shuhei Amakawa (Tokyo Tech) SR2009-48 |
We discuss the issues of present and future RF CMOS integrated circuit, which is the most significant hardware component... [more] | SR2009-48 pp.165-166 |
| ED, MW | 2008-01-17 09:45 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Examination of dual band CMOS RF power amplifier circuit Jun Kikuchi (Gunma Univ.), Hisayasu Sato (Renesas Technology Corporation), Noboru Ishihara (Gunma Univ.) ED2007-214 MW2007-145 |
Dual-band CMOS RF power amplifier circuit design techniques have been studied. In CMOS power amplifier design with low p... [more] | ED2007-214 MW2007-145 pp.45-50 |
| ED, MW | 2008-01-17 10:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Wide-Band BPSK CMOS Demodulator Circuit Yasuyuki Arai, Jun Kikuchi, Ryuichi Ujiie, Kenichi Shibata (Gunma Univ.), Tetuya Hirama, Hisayasu Sato (Renesas Technology), Noboru Ishihara (Gunma Univ.) ED2007-215 MW2007-146 |
In recent LSI systems, the wiring connections between the LSI and the LSI or the board and the board have become high de... [more] | ED2007-215 MW2007-146 pp.51-56 |
| MW, ED | 2007-01-17 10:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Vdd Gate Biasing RF CMOS Amplifier Design Technique Based on the Effect of Carrier Velocity Saturation Noboru Ishihara (Gunma Univ.) |
One of the interesting MOSFET characteristics is the effect of carrier velocity saturation (CVS) on the drain current. I... [more] | ED2006-201 MW2006-154 pp.7-12 |
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