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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 41 - 60 of 76 [Previous]  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
RECONF 2012-09-19
15:05		 Shiga Epock Ritsumei 21, Ritsumeikan Univ. Speedup of soft error tolerance evaluation with bootstrap method for FPGA systems
Kohei Takano, Yoshihiro Ichinomiya, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2012-45		 SRAM-based field programmable gate arrays (FPGAs) are vulnerable to a single event upset (SEU). Although techniques for ... [more] RECONF2012-45
pp.125-130
DC, CPSY
(Joint)		 2012-08-03
09:30		 Tottori Torigin Bunka Kaikan A development scheduling simulater for reconfiguable system
Takashige Uda, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) CPSY2012-19		 Reconfigurable Computing Systems (RC Systems) are used to high-speed applications processing. We have investigating the ... [more] CPSY2012-19
pp.61-66
RECONF 2012-05-29
15:10		 Okinawa Tiruru (Naha Okinawa, Japan) Hard error avoidance for TMR module using dynamic relocation in an FPGA
Hiroki Tanaka, Yoshihiro Ichinomiya, Sadaki Usagawa, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2012-11		 FPGA can recover from hard-error by reconfiguring itself, avoiding the hard-error part.Especially, the fault recovery ca... [more] RECONF2012-11
pp.61-66
RECONF 2012-05-29
16:00		 Okinawa Tiruru (Naha Okinawa, Japan) An Efficient Fault Detection and Avoidance Technique for FPGA Interconnects
Yuuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2012-13		 FPGA's fault detection needs a great deal of test time as compared with ASIC because FPGAs have complex structures and p... [more] RECONF2012-13
pp.71-76
RECONF 2012-05-30
10:35		 Okinawa Tiruru (Naha Okinawa, Japan) SOM-based FPGA Placement Method using Shimbel Index
Tetsuro Hamada, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2012-20		 A placement process is one of the heavily computational process in FPGA(Field Programmable Gate Array) design flow.
Al... [more]		 RECONF2012-20
pp.113-118
CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] 2012-03-03
13:30		 Miyagi   A Case Study of Supervisor Processor for Dependable System
Makoto Fujino, Yoshihiro Ichinomiya, Hiroki Tanaka, Sayaka Yoshiura, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) CPSY2011-92 DC2011-96		 Multicore processor is widely used in various systems. Although it will be used in harsh environment
such as in-vehicle... [more]		 CPSY2011-92 DC2011-96
pp.199-204
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2011-11-28
16:05		 Miyazaki NewWelCity Miyazaki Fast soft-error recovery method for duplicated softcore processor system
Yoshihiro Ichinomiya, Makoto Fujino, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2011-42		 This paper presents a technique for ensuring the reliability of the softcore processor which implemented with SRAM-based... [more] RECONF2011-42
pp.7-12
RECONF 2011-09-26
13:30		 Aichi Nagoya Univ. A Novel Cluster Structure based on Input Sharing of LUTs
Toshiya Takahashi, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2011-25		 Cluster-based FPGAs are composed of logic clusters having LUTs which are basic logic elements.
At each of logic cluster... [more]		 RECONF2011-25
pp.19-24
RECONF 2011-09-26
13:55		 Aichi Nagoya Univ. FPGA placement based on Self-Organized Map
Yasuaki Tomonari, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2011-26		 Cell placement is an important phase of current FPGA(Field Programmable Gate Array) circuit design.However, this placeme... [more] RECONF2011-26
pp.25-30
RECONF 2011-09-26
15:55		 Aichi Nagoya Univ. Relocation of Partial Reconfiguration Data for Dynamic Reconfigurable System
Sadaki Usagawa, Yoshihiro Ichinomiya, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2011-30		  [more] RECONF2011-30
pp.49-54
RECONF 2011-05-12
13:30		 Hokkaido Hokkaido Univ. (Faculty of Eng., B3 Bldg.) Context Synchronization Method for Reliable Softcore Processor System
Makoto Fujino, Noritaka Kai, Yoshihiro Ichinomiya, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2011-5		 SRAM-based FPGAs are vulnerable to a SEU,
which is induced by radiation effect.
The SEU's effects on configuration mem... [more]		 RECONF2011-5
pp.25-30
RECONF, VLD, CPSY, IPSJ-SLDM [detail] 2011-01-17
12:05		 Kanagawa Keio Univ (Hiyoshi Campus) Parallelization of the channel width search for FPGA routing
Hiroomi Sawada, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto) VLD2010-89 CPSY2010-44 RECONF2010-58		 As the FPGA becomes resourceful, the design time becomes longer.
Especially, routing process occupies the large portion... [more]		 VLD2010-89 CPSY2010-44 RECONF2010-58
pp.31-36
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2010-11-30
13:15		 Fukuoka Kyushu University A case study of the effective value range analysis for Behavioral synthesis
Kenji Tomonaga, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) CPSY2010-32		 The digital circuit becomes more complex and larger scale recently, and
behavioral synthesis that use behavioral descri... [more]		 CPSY2010-32
pp.1-6
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2010-11-30
13:35		 Fukuoka Kyushu University Examination of the virtual wiring for an ASIC emulator using high-speed serial communication
Toshio Yabuta, Yoshihiro Ichinomiya, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) CPSY2010-33		 Examination of the virtual wiring for an ASIC emulator using high-speed serial communication [more] CPSY2010-33
pp.7-12
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2010-11-30
14:35		 Fukuoka Kyushu University A case study of efficient task scheduling for FPGA-based partially reconfigurable systems
Yoshiaki Tsutsumi, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2010-43		 Dynamic Recon gurable system is the system that can build any function with recon gurable device such as FPGA (Field Pro... [more] RECONF2010-43
pp.25-30
RECONF 2010-05-13
16:20		 Nagasaki   A Case Study of Evaluation Technique for Soft Error Tolerance on SRAMs-based FPGAs.
Tsuyoshi Kimura, Noritaka Kai, Yoshiaki Tsutsumi, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2010-7		 SRAM-based field programmable gate arrays (FPGAs) are vulnerable to a single event upset (SEU),which is induced by radia... [more] RECONF2010-7
pp.37-42
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-UBI, IPSJ-MBL [detail] 2010-03-28
13:20		 Tokyo   A Case Study of Duplication Technique for SRAM-based FPGA
Kyohei Shiraishi, Motoki Amagasaki, Morihiro Kuga (Kumamoto Univ.), Nobuhisa Fujiyama, Michihiko Inukai (Toshiba), Toshinori Sueyoshi (Kumamoto Univ.) CPSY2009-90 DC2009-87		 SRAM-based Field Programmable Gate Array (FPGA) is widely used in various applications such as industrial electronic dev... [more] CPSY2009-90 DC2009-87
pp.471-476
IPSJ-SLDM, VLD, CPSY, RECONF [detail] 2010-01-26
14:55		 Kanagawa Keio Univ (Hiyoshi Campus) Design of Reconfigurable Logic Device based on Variable Grain Logic Cell
Kazuki Inoue, Yasuhiro Okamoto, Qian Zhao, Komei Yoshizawa, Hiroki Yosho, Masahiro Koga, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) VLD2009-79 CPSY2009-61 RECONF2009-64		 We propose a variable grain logic cell（VGLC）architecture. Its key feature is variable granularity which helps to create ... [more] VLD2009-79 CPSY2009-61 RECONF2009-64
pp.59-64
IPSJ-SLDM, VLD, CPSY, RECONF [detail] 2010-01-27
14:30		 Kanagawa Keio Univ (Hiyoshi Campus) Fault Recovery Technique for Softcore Processor using Partial Reconfiguration
Yoshihiro Ichinomiya, Shiro Tanoue, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) VLD2009-94 CPSY2009-76 RECONF2009-79		 This paper presents a technique for ensuring reliable softcore processor implemented on SRAM-based Field Programmable Ga... [more] VLD2009-94 CPSY2009-76 RECONF2009-79
pp.155-160
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2009-12-03
13:25		 Kochi Kochi City Culture-Plaza A Case Study of Error Correction Technique for SRAM-based FPGA using the Partial Reconfiguration
Noritaka Kai, Yoshiaki Tsutsumi, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2009-41		 The present paper describes an error correction technique for SRAM-based Field Programmable Gate Arrays (FPGAs) using th... [more] RECONF2009-41
pp.1-6
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