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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 21 - 40 of 76 [Previous]  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2015-12-02
11:15		 Nagasaki Nagasaki Kinro Fukushi Kaikan A Study of HW/SW Co-design Framework based on the Virtualization Technology
Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2015-52		 One challenge for the heterogeneous computing with the FPGA is to bridge the development gap between SW and HW design. T... [more] RECONF2015-52
pp.21-26
RECONF 2015-09-18
09:25		 Ehime Ehime University Trax solver based on machine-learned evaluation function
Takuya Nakamichi, Yusuke Sonoda, Takayuki Matsuzaki, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2015-33		 We develop a solver of board game Trax. Our basic strategy is a common game tree search algorithm. We explore the best m... [more] RECONF2015-33
pp.7-12
RECONF 2015-06-19
12:00		 Kyoto Kyoto University An Area Optimization of 3D FPGA with high speed inter-layer communication link
Yuto Takeuchi, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ) RECONF2015-4		 Three-dimensional (3D) stacking technology is attractive for providing another way to improve the performance of the lar... [more] RECONF2015-4
pp.17-22
RECONF 2015-06-20
16:15		 Kyoto Kyoto University A Technology Mapping Method for Scalable Logic Module
Ryo Araki, Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ) RECONF2015-27		 In order to implement logic functions, conventional field-programmable gate arrays (FPGAs) employs look-up tables (LUTs)... [more] RECONF2015-27
pp.147-152
RECONF, CPSY, VLD, IPSJ-SLDM [detail] 2015-01-29
11:05		 Kanagawa Hiyoshi Campus, Keio University Exploring 3D FPGA Architectures to Minimize the Number of Inter-layer Connections
Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) VLD2014-120 CPSY2014-129 RECONF2014-53		 The 3D IC technology is being researched to build better performance LSIs in a variety of applications when the process ... [more] VLD2014-120 CPSY2014-129 RECONF2014-53
pp.41-46
RECONF, CPSY, VLD, IPSJ-SLDM [detail] 2015-01-30
14:20		 Kanagawa Hiyoshi Campus, Keio University Reliability Management in 2-layered Supervisor Processor
Daiki Yamamoto, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ) VLD2014-144 CPSY2014-153 RECONF2014-77		 Computer systems are not only used in consumer electronics such as mobile phones and televisions but various industria... [more] VLD2014-144 CPSY2014-153 RECONF2014-77
pp.199-204
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2014-11-27
16:00		 Oita B-ConPlaza Design and Evaluation of High-speed Serial Communication Mechanism for FPGA-based ASIC Emulator
Takashi Okamoto, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2014-42		 The circuit scale of Application Specific Integrated Circuit（ASIC）has been increasing. Therefore the shortening of funct... [more] RECONF2014-42
pp.45-50
RECONF 2014-09-18
14:10		 Hiroshima   Prototype of fault tolerant FPGA using 65nm CMOS process
Motoki Amagasaki, Takuya Kajiwara, Kentaro Fujisawa, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2014-18		 我々はSoC（System on a Chip）に搭載されるFPGA-IP（Field Programmable Gate Array Intellectual
Property）コアに焦点をあてたFT-FPGA（Fault Tolera... [more]		 RECONF2014-18
pp.7-12
RECONF 2014-09-18
14:35		 Hiroshima   A study of run-time fault detection mechanism for fault-tolerant FPGAs
Kentaro Fujisawa, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2014-19		 The fault detection is very important for high reliability system LSI. In this paper, we propose a dynamic fault detecti... [more] RECONF2014-19
pp.13-18
RECONF 2014-06-12
11:15		 Miyagi Katahira Sakura Hall Three-dimensional FPGA Structure using High-speed Serial Communication
Takuya Kajiwara, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2014-7		 The three-dimensional (3D) integrated circuit technology is expected to continually improve the LSI (Large Scale Integra... [more] RECONF2014-7
pp.31-36
RECONF 2014-06-12
14:10		 Miyagi Katahira Sakura Hall Zyndroid: HW/SW Coprocessing Platform for Android Applications
Susumu Mashimo, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2014-10		 Nowadays, high performance of Android systems is required because the embedded systems are used in several fields and th... [more] RECONF2014-10
pp.49-54
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2013-11-28
08:55		 Kagoshima   Mapping of Java bytecode to virtual CGRA with implementation in FPGA
Yuki Ogawa, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2013-47		 In embedded systems, the needs for rapid both low-cost development and high performance has been increasing recently.
... [more]		 RECONF2013-47
pp.45-50
RECONF 2013-09-19
09:25		 Ishikawa Japan Advanced Institute of Science and Technology A LUT Architecture Based on Partial Function of Shannon Expansion
Kyosei Yanagida, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2013-27		 In order to implement logic functions, conventional eld programmable gate arrays (FPGAs) employs look-up tables (LUTs) ... [more] RECONF2013-27
pp.43-48
SIP, CAS, MSS, VLD 2013-07-11
18:00		 Kumamoto Kumamoto Univ. SOM Based FPGA Placement Method Considering Wire Segment Length
Tetsuro Hamada, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) CAS2013-16 VLD2013-26 SIP2013-46 MSS2013-16		 A placement process is one of the heavily computational process in FPGA(Field Programmable Gate Array) design flow.
Al... [more]		 CAS2013-16 VLD2013-26 SIP2013-46 MSS2013-16
pp.83-88
RECONF 2013-05-21
10:10		 Kochi Kochi Prefectural Culture Hall Design and Evaluation of FPGA-based ASIC Emulator using High-speed Serial Communication
Takashige Uda, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2013-10		 Recently, development period of ASIC is longer becouse of the increase in circuit scale.
Verification process accounts ... [more]		 RECONF2013-10
pp.49-54
RECONF 2013-05-21
11:25		 Kochi Kochi Prefectural Culture Hall A defect-robust FPGA-IP core architecture
Motoki Amagasaki, Kazuki Inoue, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2013-13		 In this paper, we propose fault-tolerant FPGA -IP cores for system LSI. Unlike discrete FPGAs, in
which the integration... [more]		 RECONF2013-13
pp.67-72
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-16
10:00		 Kanagawa   A Study of 3D FPGA Architecture Using Face-to-Face Stacked Routing Layer
Yusuke Iwai, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) VLD2012-109 CPSY2012-58 RECONF2012-63		 3D LSIs promise More than Moore integration by packing a great deal of functionality on a chip, while improving performa... [more] VLD2012-109 CPSY2012-58 RECONF2012-63
pp.13-18
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2012-11-27
14:15		 Fukuoka Centennial Hall Kyushu University School of Medicine A study on reconfigurable direct conversion JAVA accelerator for embedded systems
Seiya Takada, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ) RECONF2012-48		 In embedded systems, the requirements for short-time and low-cost development have been increased
recently. For this re... [more]		 RECONF2012-48
pp.9-14
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2012-11-28
09:00		 Fukuoka Centennial Hall Kyushu University School of Medicine A Basic Study of FPGA Routing Architecture Based on Scale Free Network
Satoshi Hayama, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2012-50		 FPGA(Fiele Programmable Gate Array) has many routing resources in order to provide the flexibility.
These routing resou... [more]		 RECONF2012-50
pp.17-22
RECONF 2012-09-18
15:15		 Shiga Epock Ritsumei 21, Ritsumeikan Univ. An Area Minimized Logic Cluster using COGRE Logic Cell
Toshiya Takahashi, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2012-32		 These days, FPGAs (Field Programmable Gate Arrays) is required to increase in size and performance
in order to deal w... [more]		 RECONF2012-32
pp.49-54
 Results 21 - 40 of 76 [Previous]  /  [Next]  
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