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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC | 2013-12-13 13:00 |
Ishikawa | Efficient Scan-Based BIST Architecture for Application-Dependent FPGA Test Keita Ito, Tomokazu Yoneda, Yuta Yamato, Kazumi Hatayama, Michiko Inoue (NAIST)  DC2013-68 |
This paper presents a scan-based BIST architecture for testing of application-dependent circuits configured on FPGA. I... [more] |
DC2013-68 pp.1-6 |
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| DC | 2013-02-13 16:40 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Data volume reduction method for unknown value handling in built-in self test used in field Yuta Yoshimi (NAIST), Kazumi Hatayama, Yuta Yamato, Tomokazu Yoneda, Michiko Inoue (NAIST/JST) DC2012-90 |
Many approaches on test pattern compression targeted unknown value handling. It is because unknown values have impacts o... [more] | DC2012-90 pp.61-66 |
| DC | 2012-06-22 16:10 |
Tokyo | Room B3-1 Kikai-Shinko-Kaikan Bldg | On Per-Cell Dynamic IR-Drop Estimation in At-Speed Scan Testing Yuta Yamato, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue (NAIST) DC2012-15 |
It is well known that dynamic IR-drop analysis consumes large amount of time even for a few clock cycles. This paper add... [more] | DC2012-15 pp.39-44 |
| DC | 2012-02-13 15:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Dynamic Test Scheduling for In-Field Aging Detection Yosuke Morinaga, Tomokazu Yoneda (NAIST), Hyunbean Yi (Hanbat National Univ.), Michiko Inoue (NAIST) DC2011-85 |
[more] | DC2011-85 pp.55-60 |
| DC | 2011-02-14 11:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Pattern Generation Method to Uniform Initial Temperature of Test Application Emiko Kosoegawa, Tomokazu Yoneda, Michiko Inoue, Hideo Fujiwara (NAIST/JST) DC2010-63 |
Circuit failure prediction is essential to ensure product quality and in-field reliability. The basic principle of circu... [more] | DC2010-63 pp.27-32 |
| DC | 2011-02-14 13:45 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Test Pattern Generation for Highly Accurate Delay Testing Keigo Hori (NAIST), Tomokazu Yoneda, Michiko Inoue, Hideo Fujiwara (NAIST/JST) DC2010-64 |
We propose a new faster-than-at-speed test method to detect small delay defects. As semiconductor technology is scaling ... [more] | DC2010-64 pp.33-38 |
| ICD (Workshop) |
2010-08-16 - 2010-08-18 |
Overseas | Ho Chi Minh City University of Technology | [Invited Talk]
Circuit Failure Prediction by Field Test (DART) with Delay-Shift Measurement Mechanism Yasuo Sato, Seiji Kajihara (Kyusyu Institute of Technology), Michiko Inoue, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara (NAIST), Yukiya Miura (Tokyo Metropolitan Univ.) |
The main task of test had traditionally been screening of hard defects before shipping. However, current chips are takin... [more] | |
| DC | 2010-06-25 13:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Full Scan Design Method for Asynchronous Sequential Circuits Based on C-element Scan Paths Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara (NAIST) DC2010-8 |
Using asynchronous VLSI designs resolve synchronous circuit design difficulties, e.g.\ the clock skew, higher throughput... [more] | DC2010-8 pp.1-6 |
| DC | 2010-02-15 09:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Test Pattern Re-Ordering for Thermal-Uniformity during Test Makoto Nakao, Tomokazu Yoneda, Michiko Inoue, Hideo Fujiwara (Nara Inst. of Sci and Tech.) DC2009-66 |
Power consumption during VLSI testing varies spatially and temporally, and it leads to temperature variation during tes... [more] | DC2009-66 pp.7-12 |
| DC | 2010-02-15 14:35 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Seed Selection for High Quality Delay Fault Test in BIST Akira Taketani, Tomokazu Yoneda, Michiko Inoue, Hideo Fujiwara (Nara Inst. of Sci and Tech.) DC2009-74 |
In this paper, we target a scan BIST architecture that consists of LFSR, phase shifter and MISR, and propose a method to... [more] | DC2009-74 pp.57-62 |
| DC | 2009-02-16 15:45 |
Tokyo | Resource Binding to Minimize the Number of RTL Paths Yuichi Uemoto, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara (Nara Inst. of Scie and Tech.) DC2008-77 |
Though path delay testing is promising to detect small delay in a VLSI circuit, it has a practical problem that the numb... [more] | DC2008-77 pp.55-60 |
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| DC | 2008-02-08 11:40 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Secure Scan Design Based on Ballanced Structure Muneo Hasegawa, Michiko Inoue, Hideo Fujiwara (NAIST) DC2007-73 |
In this paper, we propose a secure scan design which protects scan-based side channel attacks to the circuits containing... [more] | DC2007-73 pp.39-44 |
| DC | 2008-02-08 14:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | RTL False Path Identification Using High Level Synthesis Information Naotsugu Ikeda, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara (NAIST) DC2007-77 |
This paper proposes a method of RTL false path identification using high level synthesis information. By using the false... [more] | DC2007-77 pp.63-68 |
| ICD, IPSJ-ARC | 2006-06-08 15:30 |
Kanagawa | Design for Testability of Software-Based Self-Test for Processors Masato Nakazato, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara (NAIST) |
In this paper, we propose a design for testability method for test programs of software-based self-test using test progr... [more] | ICD2006-48 pp.49-54 |
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