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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD | 2016-03-01 17:05 |
Okinawa | Okinawa Seinen Kaikan | Low-power Standard Cell Memory using Silicon-on-Thin-BOX (SOTB) and Body-bias Control Yusuke Yoshida, Masaru Kudo, Kimiyoshi Usami (SIT)  VLD2015-130 |
In recent years, energy harvesting and sensor node have attracted a lot of attention. Therefore, a memory which can redu... [more] | VLD2015-130 pp.111-116 |
| VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] | 2016-01-20 09:25 |
Kanagawa | Hiyoshi Campus, Keio University | Implementation and evaluation of Dynamic Multi-Vth methodology in Silicon-on-Thin-BOX Shohei Io, Hanano Suzuki, Shohei Nakamura, Kimiyoshi Usami (Shibaura IT) VLD2015-88 CPSY2015-120 RECONF2015-70 |
Silicon-on-Thin-BOX is one of the FD-SOI devices. It operates at ultra-low voltage and it is possible to effectively cha... [more] | VLD2015-88 CPSY2015-120 RECONF2015-70 pp.91-96 |
| ICD, CPSY | 2015-12-18 13:30 |
Kyoto | Kyoto Institute of Technology | Power optimization based on a simple power model for a micro-controller Hayate Okuhara, Yu Fujita, Kuniaki Kitamori (Keio Univ.), Kimiyoshi Usami (Shibaura Institute of Tech.), Hideharu Amano (Keio Univ.) ICD2015-88 CPSY2015-101 |
[more] | ICD2015-88 CPSY2015-101 pp.93-98 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 16:20 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Sleep Control Using Virtual Ground Voltage Detection For Fine-Grain Power Gating Masaru Kudo, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2015-57 DC2015-53 |
This paper describes a sleep control technique using leakage monitor circuit to implement Fine-Grain Power Gating (FGPG)... [more] | VLD2015-57 DC2015-53 pp.129-134 |
| VLD | 2015-03-04 09:40 |
Okinawa | Okinawa Seinen Kaikan | Ground Bounce Suppressive Effect using Power Switch Driver to control Power Switch Rise Time Tetsutaro Ohnishi, Kimiyoshi Usami (S.I.T.) VLD2014-176 |
While Power Gating technology enables us to reduce leakage current, it causes a serious problem of occurring Ground Boun... [more] | VLD2014-176 pp.129-134 |
| VLD | 2015-03-04 11:10 |
Okinawa | Okinawa Seinen Kaikan | Energy minimization by voltage choice targeted for logic synthesis in silicon on thin buried oxide Jun Kawasaki, Kimiyoshi Usami (S.I.T.) VLD2014-179 |
Silicon on Thin Buried Oxide (SOTB) technology enables us to reduce supply voltage because the Vth variation can be supp... [more] | VLD2014-179 pp.147-152 |
| RECONF, CPSY, VLD, IPSJ-SLDM [detail] | 2015-01-29 17:00 |
Kanagawa | Hiyoshi Campus, Keio University | Temperature sensor applying Body Bias in Silicon-on-Thin-BOX Tsubasa Kosaka, Shohei Nakamura, Kimiyoshi Usami (S.I.T.) VLD2014-127 CPSY2014-136 RECONF2014-60 |
The performance advancement by the transistor scaling is blocked by increase of power consumption and process variation.... [more] | VLD2014-127 CPSY2014-136 RECONF2014-60 pp.99-104 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 09:15 |
Oita | B-ConPlaza | Design of Flip-Flop with Timing Error Tolerance Taito Suzuki, Youhua Shi, Nozomu Togawa (Waseda Univ.), Kimiyoshi Usami (SIT), Masao Yanagisawa (Waseda Univ.) VLD2014-79 DC2014-33 |
Under the influence of the miniaturization of the integrated circuit, the variation of the operation condition of the ci... [more] | VLD2014-79 DC2014-33 pp.45-50 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 16:15 |
Oita | B-ConPlaza | High speed design of sub-threshold circuit by using DTMOS Yuji Fukudome, Youhua Shi, Nozomu Togawa (Waseda Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech), Masao Yanagisawa (Waseda Univ.) VLD2014-88 DC2014-42 |
Low power consumption is achieved by operating circuits in sub-threshold region. However, in sub-threshold region, the... [more] |
VLD2014-88 DC2014-42 pp.117-121 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 15:35 |
Oita | B-ConPlaza | Energy-efficient High-level Synthesis Algorithm targeting HDR-mcv Architecture with Multiple Clock Domains and Multiple Supply Voltages Shin-ya Abe, Youhua Shi (Waseda Univ.), Kimiyoshi Usami (Shibaura Institute of Technology/Waseda Univ.), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-102 DC2014-56 |
An HDR-mcv architecture, which integrates multiple supply voltages and multiple clock domains into high-level synthesis ... [more] | VLD2014-102 DC2014-56 pp.203-208 |
| IE, ICD, VLD, IPSJ-SLDM [detail] | 2014-10-02 13:25 |
Miyagi | Local pulse generation in variable stages pipeline designs for low energy consumption Takayuki Nii, Youhua Shi, Nozomu Togawa (Waseda Univ.), Kimiyoshi Usami (Shibaura Inst. of Univ.), Masao Yanagisawa (Waseda Univ.) VLD2014-61 ICD2014-54 IE2014-40 |
The increase of energy consumption due to improved performance has become a problem in the mobile terminal, and various ... [more] | VLD2014-61 ICD2014-54 IE2014-40 pp.7-12 |
|
| ICD, SDM | 2014-08-04 09:00 |
Hokkaido | Hokkaido Univ., Multimedia Education Bldg. | [Invited Talk]
A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14μA Sleep Current using Reverse-Body-Bias Assisted 65nm SOTB CMOS Technology Koichiro Ishibashi (UEC), Nobuyuki Sugii (LEAP), Kimiyoshi Usami (SIT), Hideharu Amano (KU), Kazutoshi Kobayashi (KIT), Cong-Kha Pham (UEC), Hideki Makiyama, Yoshiki Yamamoto, Hirofumi Shinohara, Toshiaki Iwamatsu, Yasuo Yamaguchi, Hidekazu Oda, Takumi Hasegawa, Shinobu Okanishi, Hiroshi Yanagita (LEAP) SDM2014-62 ICD2014-31 |
[more] | SDM2014-62 ICD2014-31 pp.1-4 |
| CPSY, DC (Joint) |
2014-07-30 18:15 |
Niigata | Toki Messe, Niigata | Design of OpenCL Library and Execution Dispatcher for Embedded Accelerator Ryuichi Sakamoto, Mikiko Sato (Tokyo Univ. of Agriculture and Tech. (TUAT)), Hideharu Amano, Tadahiro Kuroda (Keio Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech.), Hiroshi Nakamura (Univ. of Tokyo), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech. (TUAT)) CPSY2014-46 |
Recently, an embedded processor for use in smartphones and other devices is equipped with some power-efficient accelerat... [more] | CPSY2014-46 pp.215-220 |
| VLD | 2014-03-05 13:00 |
Okinawa | Okinawa Seinen Kaikan | Investigation of thermal monitor for applying to Dynamic Voltage Scaling in SOTB Tatsuya Wada, Kimiyoshi Usami (Shibaura Inst. of Tech) VLD2013-160 |
SOTB (Silicon on Thin Buried Oxide) transistors can operate at high speed in the ultra-low voltage. However, variation i... [more] | VLD2013-160 pp.141-146 |
| VLD | 2014-03-05 13:25 |
Okinawa | Okinawa Seinen Kaikan | Experiment and Analysis on Temperature Dependence of Delay and Energy for Subthreshold Circuits Hiroki Kushida, Youhua Shi, Nozomu Togawa (Waseda Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech.), Masao Yanagisawa (Waseda Univ.) VLD2013-161 |
Low voltage design has been used in order to reduce the energy dissipation of mobile network equipment. However, as supp... [more] | VLD2013-161 pp.147-151 |
| VLD | 2014-03-05 13:50 |
Okinawa | Okinawa Seinen Kaikan | Design methodology on Dynamic Multi-Vth control technique for Silicon on Thin Buried Oxide(SOTB) Tatsuki Saigusa, Kimiyoshi Usami (Shibaura Inst. of Tech) VLD2013-162 |
Silicon on thin BOX(SOTB) is one of FD-SOI device.It is possible to operate with ultra-low voltage of 0.4V and greatly c... [more] | VLD2013-162 pp.153-158 |
| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-29 15:40 |
Kanagawa | Hiyoshi Campus, Keio University | Methodology for NBTI measurement using an on-chip leakage monitor circuit Takaaki Sato, Kimiyoshi Usami (Shibaura Inst. of Tech.) VLD2013-131 CPSY2013-102 RECONF2013-85 |
Miniaturization in recent years ,LSI's aging has become prominent as a factor that prevents the normal operation.By meas... [more] | VLD2013-131 CPSY2013-102 RECONF2013-85 pp.173-178 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 10:25 |
Kagoshima | Development of a fine-grain power-gated CPU "Geyser-3" and adaptive power-off control to the temperature Kimiyoshi Usami, Masaru Kudo, Kensaku Matsunaga, Tsubasa Kosaka, Yoshihiro Tsurui (Shibaura Inst. of Tech.), Weihan Wang, Hideharu Amano (Keio Univ), Ryuichi Sakamoto, Mitaro Namiki (Tokyo Univ of Agriculture and Tech), Masaaki Kondo (Univ of Elec-Comm), Hiroshi Nakamura (Univ of Tokyo) VLD2013-80 DC2013-46 |
[more] | VLD2013-80 DC2013-46 pp.135-140 |
|
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-29 11:40 |
Kagoshima | Clock Energy-efficient High-level Synthesis and Experimental Evaluation for HDR-mcd Architecture Shin-ya Abe, Youhua Shi (Waseda Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech./Waseda Univ.), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-97 DC2013-63 |
In this paper, we propose a clock energy-efficient high-level synthesis algorithm for HDR-mcd architecture. In HDR-mcd,... [more] |
VLD2013-97 DC2013-63 pp.263-268 |
|
| CPSY | 2013-10-03 11:35 |
Chiba | Makuhari Messe | A Chip Evaluation of Cube-1: A multi-core processor with 3D TCI Hideharu Amano, Yusuke Koizumi (Keio Univ.), Noriyuki Miura (Kobe Univ.), Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda (Keio Univ.), Ryuichi Sakamoto, Mitaro Namiki (Tokyo Agri. and Tech.), Kimiyoshi Usami, Masaaki Kondo (Univ. of Elect. Comm.), Hiroshi Nakamura (Univ. of Tokyo) CPSY2013-33 |
[more] | CPSY2013-33 pp.13-18 |
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