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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] | 2020-01-24 13:55 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Edge detection algorithms using stochastic architectures for various images Naoto Shinozaki, Kimiyoshi Usami (SIT)  VLD2019-87 CPSY2019-85 RECONF2019-77 |
Stochastic computing (SC) is an approximate calculation method with the existence probability of 1 in a bit string as a ... [more] | VLD2019-87 CPSY2019-85 RECONF2019-77 pp.199-204 |
| VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2019-11-13 15:00 |
Ehime | Ehime Prefecture Gender Equality Center | On-Chip Leakage Monitor based Temperature Sensor Circuit for Ultra Low Voltage Daisuke Sato, Kimiyoshi Usami (SIT) VLD2019-33 DC2019-57 |
The increase in leakage current due to miniaturization is a big problem in devices that require low power consumption. L... [more] | VLD2019-33 DC2019-57 pp.45-50 |
| VLD, IPSJ-SLDM | 2019-05-15 14:20 |
Tokyo | Ookayama Campus, Tokyo Institute of Technology | Approximate Computing Technique Using Memoization and Simplified Multiplication Yoshinori Ono, Kimiyoshi Usami (SIT) VLD2019-2 |
In embedded systems, approximate computing can strongly promote reduction of execution time and energy consumption in ex... [more] | VLD2019-2 pp.13-18 |
| HWS, VLD | 2019-02-28 10:00 |
Okinawa | Okinawa Ken Seinen Kaikan | Thermal transient analysis and evaluation of the heat generation and dissipation in three-dimensional stacked LSI Ryota Horigome, Kimiyoshi Usami (Shibaura Inst. of Tech.) VLD2018-107 HWS2018-70 |
As a technology for improving the degree of integration of LSI, there is a three-dimensional stacking technology of LSI ... [more] | VLD2018-107 HWS2018-70 pp.85-90 |
| HWS, VLD | 2019-02-28 10:25 |
Okinawa | Okinawa Ken Seinen Kaikan | Evaluation of low power consumption Standard Cell Memory (SCM) using body-bias control in Silicon-on-Thin-BOX MOSFET:SOTB Ryo Magasaki, Yusuke Yoshida (Shibaura Inst. of Tech.), Hideharu Amano (Keio Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech.) VLD2018-108 HWS2018-71 |
In recent years, IoT devices are rapidly increasing. One of the IoT devices is a sensor node and a small medical device... [more] | VLD2018-108 HWS2018-71 pp.91-96 |
| CPSY, DC, IPSJ-ARC (Joint) [detail] |
2018-08-01 18:30 |
Kumamoto | Kumamoto City International Center | Takeharu Ikezoe, Hideharu Amano (Keio Univ.), Junya Akaike, Kimiyoshi Usami, Masaru Kudo (SIT), Keizo Hiraga, Yusuke Shuto, Kojiro Yagami (Sony SS) CPSY2018-32 |
[more] | CPSY2018-32 pp.229-234 |
| VLD, IPSJ-SLDM | 2018-05-16 15:00 |
Fukuoka | Kitakyushu International Conference Center | Non-volatile Power Gating for Data Cache with Dynamic Line-selection Sosuke Akiba, Kimiyoshi Usami (SIT) VLD2018-2 |
In the whole of CPU, the proportion of energy consumption of the cache is increasing. Non-volatile Power Gating(NVPG) is... [more] | VLD2018-2 pp.19-24 |
| VLD, HWS (Joint) |
2018-03-02 09:50 |
Okinawa | Okinawa Seinen Kaikan | Approximate computing based on extension of DRAM refresh interval and data correction Takamasa Fukasawa, Kimiyoshi Usami (SIT) VLD2017-121 |
As DRAM capacity increases, there is concern that energy consumption will increase due to the refresh. Therefore, we pro... [more] | VLD2017-121 pp.193-198 |
| VLD, HWS (Joint) |
2018-03-02 10:30 |
Okinawa | Okinawa Seinen Kaikan | Implementation of Reconfigurable Accelerator Cool Mega-Array Using MTJ-based Nonvolatile Flip-Flop Enabling to Verify Stored Data Junya Akaike, Kimiyoshi Usami, Masaru Kudo (SIT), Hideharu Amano, Takeharu Ikezoe (Keio Univ.), Keizo Hiraga, Yusuke Shuto, Kojiro Yagami (Sony SS) VLD2017-122 |
As a method of reducing the power consumption of the flip-flop circuit, there is a nonvolatile flip-flop (NVFF) that ena... [more] | VLD2017-122 pp.199-204 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 14:55 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | Leakage Energy Reduction for Digital Embedded Memory using Dynamic Multi Body Bias Control Yusuke Yoshida, Kimiyoshi Usami (SIT) VLD2017-33 DC2017-39 |
Embedded memory macros are major central building blocks of any microprocessor and greatly affect power dissipation. In ... [more] | VLD2017-33 DC2017-39 pp.37-42 |
| VLD | 2017-03-01 14:00 |
Okinawa | Okinawa Seinen Kaikan | Fine-Grain Power Gating of MTJ-based Non-volatile Cache and Dynamic Selection Control for Storing Cache Lines Shota Enokido, Kimiyoshi Usami (SIT) VLD2016-102 |
Non-volatile Power Gating(NVPG) is a technique to power gate memory elements to reduce leakage power while keeping the s... [more] | VLD2016-102 pp.1-6 |
| VLD | 2017-03-01 14:25 |
Okinawa | Okinawa Seinen Kaikan | A Nonvolatile Flip-Flop Circuit with a Split Store/Restore Architecture for Power Gating Masaru Kudo, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2016-103 |
This paper describes a nonvolatile Flip-Flop (NVFF) circuit to implement Nonvolatile Power Gating. We proposed a new NVF... [more] | VLD2016-103 pp.7-12 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-25 10:15 |
Kanagawa | Hiyoshi Campus, Keio Univ. | MTJ-based Nonvolatile Flip-Flop Circuit Enabling to Verify Stored Data Junya Akaike, Kimiyoshi Usami (SIT) VLD2016-97 CPSY2016-133 RECONF2016-78 |
With the spread of portable devices in recent year, products with high performance and low power consumption are require... [more] | VLD2016-97 CPSY2016-133 RECONF2016-78 pp.175-180 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-25 10:55 |
Kanagawa | Hiyoshi Campus, Keio Univ. | Thermal transient analysis and evaluation of three-dimensional stacked chips Shogo Yasuda, Kimiyoshi Usami (SIT) VLD2016-98 CPSY2016-134 RECONF2016-79 |
There is a three-dimensional stacking technology of LSI in technology for improving the density of LSI. Three-dimensiona... [more] | VLD2016-98 CPSY2016-134 RECONF2016-79 pp.181-186 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-28 13:10 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Feasibility studies and evaluation for Level-Shifter less design in Silicon-on-Thin-BOX (SOTB) Shunsuke Kogure, Kimiyoshi Usami (Shibaura Institute of Tech) VLD2016-47 DC2016-41 |
Level shifter is a circuit that changes the voltage amplitude of the signal. It is essential to exchange signals with di... [more] | VLD2016-47 DC2016-41 pp.19-24 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-29 09:00 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Design and Implementation Methodology of Low-power Standard cell memory with optimized body-bias separation in Silicon-on-Thin-BOX (SOTB) Yusuke Yoshida, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2016-53 DC2016-47 |
We focus on the Standard Cell Memory (SCM) as another option to supersede SRAM for low-voltage operation. This paper des... [more] | VLD2016-53 DC2016-47 pp.55-60 |
| VLD, CAS, MSS, SIP | 2016-06-17 09:30 |
Aomori | Hirosaki Shiritsu Kanko-kan | Line selection to reduce store-energy in MTJ-based non-volatile caches Takamasa Fukasawa, Kimiyoshi Usami (SIT) CAS2016-18 VLD2016-24 SIP2016-52 MSS2016-18 |
There is a technique of power gating for reducing the energy consumption of the cache. The technique is a combination of... [more] | CAS2016-18 VLD2016-24 SIP2016-52 MSS2016-18 pp.97-102 |
| VLD, CAS, MSS, SIP | 2016-06-17 09:50 |
Aomori | Hirosaki Shiritsu Kanko-kan | Design and Evaluation of MTJ-based Standard Cell Memory Junya Akaike, Masaru Kudo, Kimiyoshi Usami (SIT) CAS2016-19 VLD2016-25 SIP2016-53 MSS2016-19 |
With the spread of portable devices, products with high performance and long battery life are required. In this paper, w... [more] | CAS2016-19 VLD2016-25 SIP2016-53 MSS2016-19 pp.103-108 |
| VLD | 2016-03-01 16:15 |
Okinawa | Okinawa Seinen Kaikan | Noise reduction effect for input dependence of Zigzag Power Gating Tadahiro Kanamoto, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2015-128 |
In Power Gating techniques to reduce leakage current, there is the technology called Zigzag Power Gating. Zigzag Power G... [more] | VLD2015-128 pp.99-103 |
| VLD | 2016-03-01 16:40 |
Okinawa | Okinawa Seinen Kaikan | Optimization technique of substrate voltage for Dynamic Multi-Vth methodology in Silicon-on-thin BOX. Hanano Suzuki, Kimiyoshi Usami (Shibaura IT) VLD2015-129 |
Silicon-on-Thin-BOX is one of the FD-SOI devices. It operates at ultra-low voltage and it is possible to effectively cha... [more] | VLD2015-129 pp.105-110 |
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