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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-26 14:30 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | Proposal of Speculative Memory Access Mechanism Based on Snoop Cache Yuji Sekiguchi, Hiroyoshi Jutori, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.)  CPSY2012-47 |
Ratio of execution path is mostly dominated by up to two execution paths in program loops. We have developed the specula... [more] | CPSY2012-47 pp.1-6 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-26 14:55 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | A Study of Path Prediction Mechanism for Improving Accuracy by using Detailed History Information Hiroyoshi Jutori, Takanobu Baba, Takeshi Ohkawa, Kanemitsu Ootsu, Takashi Yokota (Utsunomiya Univ.) CPSY2012-48 |
Speculative multithreading expects speed-up for programs that have complicated dependency. To achieve high performance ... [more] |
CPSY2012-48 pp.7-12 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-28 13:00 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | A Case Study of Short-term Development of Cooperation with FPGA-based System by Introducing Distributed-object ORB Engine Takeshi Ohkawa, Soshi Takano, Daichi Uetake, Takashi Yokota, Kanemitsu Ootsu, Takanobu Baba (Utsunomiya Univ.) RECONF2012-56 |
We are developing “ORB Engine” which is a distributed-object middleware suitable for an FPGA, in order to reduce the ter... [more] | RECONF2012-56 pp.51-56 |
| DC, CPSY (Joint) |
2012-08-02 13:30 |
Tottori | Torigin Bunka Kaikan | Effect of Loop Unrolling for Two-Path Limited Speculation Method Yuki Homma, Hiroyoshi Jutori, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.) CPSY2012-9 |
Our Two-Path Limited Speculation system PALS speculatively executes one of the top two paths of high frequency in loops.... [more] | CPSY2012-9 pp.1-6 |
| DC, CPSY (Joint) |
2012-08-02 14:00 |
Tottori | Torigin Bunka Kaikan | Consideration of Loop Path Predictors based on Branch Prediction Methods Kazuhiro Kinkai, Hiroyoshi Jutori, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.) CPSY2012-10 |
Execution path ratio is mostly dominated by up to two execution paths in program loops. We consider the Two-Path Limited... [more] | CPSY2012-10 pp.7-12 |
| DC, CPSY (Joint) |
2011-07-29 11:35 |
Kagoshima | A Study of Dynamic Modification of Optimal Paths Speculation for Two-Path Limited Speculation Method Hiroyoshi Jutori (Utsunomiya Univ.), Tsubasa Tsuda (SKI Co.,Ltd.), Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.) CPSY2011-14 |
Thread-level speculative execution expects speed-up for programs that have complicated dependency. We focus on a change... [more] |
CPSY2011-14 pp.31-36 |
|
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-12-01 09:50 |
Fukuoka | Kyushu University | Preliminary Evaluation of Automatic Thread-Level Parallelization using Binary-Level Variable Analysis Takashi Shiroto, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.) CPSY2010-37 |
Recently, the multi-core processors are widely available. For effective utilization of the performance of multi-core pr... [more] |
CPSY2010-37 pp.31-36 |
| CPSY, DC (Joint) |
2010-08-03 - 2010-08-05 |
Ishikawa | Kanazawa Cultural Hall | A Consideration of Speculative Memory Access in Two-Path Limited Speculation System Hiroyoshi Jutori, Akihiro Fukuda, Tsubasa Tsuda, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.) CPSY2010-18 |
We have proposed two-path limited speculation method and a multi-core processor architecture PALS which based on the met... [more] | CPSY2010-18 pp.61-66 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-03 11:20 |
Kochi | Kochi City Culture-Plaza | Proposal of Multi-Core Processor PALS to Realize Two-Path Limited Speculation Method Hiroyoshi Jutori, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.) CPSY2009-46 |
We have proposed a two-path limited speculation method for higher performance execution of program's loop. This method s... [more] | CPSY2009-46 pp.19-24 |
| RECONF | 2009-09-17 16:40 |
Tochigi | Utsunomiya Univ. | [Invited Talk]
YAWARA: A Self-Optimizing Computer System Project Takanobu Baba, Kanemitsu Ootsu, Takashi Yokota (Utsunomiya Univ.) RECONF2009-27 |
The YAWARA project aims at an extreme optimization system that reconfigures both hardware and software at run-time. This... [more] | RECONF2009-27 pp.49-54 |
| CPSY, DC (Joint) |
2009-08-04 - 2009-08-05 |
Miyagi | Pipelined Multithreading with Clustered Communication on Commodity Multi-Core Processors *Yuanming Zhang, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.) CPSY2009-26 |
Recently proposed pipelined multithreading (PMT) techniques have shown great applicability to parallelizing general prog... [more] | CPSY2009-26 pp.97-102 |
|
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-18 10:00 |
Fukuoka | Kitakyushu Science and Research Park | A Path-Based Thread Partitioning Technique Considering Loop Structures Hirohito Ogawa, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.) CPSY2008-37 |
Speed-up by the multithreaded execution is important to make use of the performance of the multi-core processor effect... [more] |
CPSY2008-37 pp.1-6 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-18 10:25 |
Fukuoka | Kitakyushu Science and Research Park | Program Behavior Analysis Based on Loop Paths Hideto Yanome, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.) CPSY2008-38 |
The well-known 90/10 locality rule indicates that a program executes about 90% of its instructions using only 10% of its... [more] | CPSY2008-38 pp.7-12 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-18 10:50 |
Fukuoka | Kitakyushu Science and Research Park | Initial Examination of Detour Routing that uses Global Information Hiroki Mori, Takashi Yokota, Kanemitsu Ootsu, Takanobu Baba (Utsunomiya Univ.) CPSY2008-39 |
Recently, massively parallel computers with many nodes appears. They aim at achieving high performance by increasing of ... [more] | CPSY2008-39 pp.13-18 |
| CPSY | 2006-12-15 10:05 |
Tokyo | Tokyo Univ. Komaba Research Campus | Fault-Tolerant Routing Algorithm Using Global Information Masaaki Ogawa, Takashi Yokota, Kanemitsu Ootsu, Takanobu Baba (Utsunomiya Univ.) |
[more] | CPSY2006-42 pp.25-30 |
| CPSY | 2006-12-15 17:00 |
Tokyo | Tokyo Univ. Komaba Research Campus | Effects of Loop Unrolling on Binary Level Multithreading Hideki Masuzawa, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.) |
[more] | CPSY2006-52 pp.69-74 |
| CPSY | 2005-12-16 13:20 |
Tochigi | Academia Hall, Utsunomiya Univ. | Design of run-time support system for binary level multithreading Kanemitsu Ootsu, Toru Iba, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.) |
Nowadays, based on the background of highly increased transistor counts availble on single chip, two or more processor c... [more] | CPSY2005-35 pp.13-18 |
| CPSY | 2005-12-16 14:25 |
Tochigi | Academia Hall, Utsunomiya Univ. | A Consideration and Evaluation of Thread Partitioning Method based on Program Structures Daisuke Mitsugi, Takahiko Kobayashi, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.) |
We have studied a system that translates single-threaded codes to multithreaded ones at binary level. It is difficult to... [more] | CPSY2005-37 pp.25-30 |
| CPSY | 2005-12-16 14:50 |
Tochigi | Academia Hall, Utsunomiya Univ. | A multithread code optimization method that considered interthread communication Noritoshi Akutsu, Hideki Masuzawa, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.) |
We have proposed a software system architecture that translates single threaded codes into the optimized multithreaded o... [more] | CPSY2005-38 pp.31-36 |
| CPSY | 2005-12-16 15:15 |
Tochigi | Academia Hall, Utsunomiya Univ. | An Extendable Simulation Environment for Chip-Multi VLIW Architecture Design Fumihito Furukawa (Teikyo Univ.), Takayuki Aoki, Daisuke Oka, Atsushi Tsukikawa, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.) |
Chip-multi VLIW architecture is promising in both of execution performance and power consumption. To explore such archit... [more] | CPSY2005-39 pp.37-42 |
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