| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 10:25 |
Kagoshima | Automatic synthesis of the inter-processor communication implimentation for hetero multiprocessor systems Yukihito Ishida, Yuki Ando, Shinya Honda, Hiroaki Takada, Masato Edahiro (Nagoya Univ.)  RECONF2013-50 |
This paper introduces an automatic synthesis technique of inter-processor communication for System-on-chip with heteroge... [more] | RECONF2013-50 pp.63-68 |
|
| CPSY, VLD, RECONF, IPSJ-SLDM [detail] | 2013-01-17 13:25 |
Kanagawa | A Channel-based Communication/Synchronization Model for SW-HW Multitasking on Dynamically Partially Reconfigurable FPGAs Krzysztof Jozwik, Shinya Honda, Masato Edahiro (Nagoya Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroaki Takada (Nagoya Univ.) VLD2012-130 CPSY2012-79 RECONF2012-84 |
Dynamically Partially Reconfigurable (DPR) FPGAs allow for implementation of a concept of SW-HW multitasking where flow ... [more] | VLD2012-130 CPSY2012-79 RECONF2012-84 pp.135-140 |
|
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-26 10:30 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | Automated Identification of Performance Bottleneck on Embedded Systems for Architecture Exploration Yuki Ando (Nagoya Univ.), Seiya Shibata (NEC), Shinya Honda (Nagoya Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroaki Takada (Nagoya Univ.) VLD2012-62 DC2012-28 |
This paper presents a method to identify performance bottleneck on an embedded systems. At the same time, our method exp... [more] | VLD2012-62 DC2012-28 pp.19-24 |
| WBS | 2012-07-26 11:30 |
Aichi | Nagoya Univ. | [Invited Talk]
TBD Hiroaki Takada (Nagoya Univ.) |
[more] | |
| RECONF | 2012-05-29 16:45 |
Okinawa | Tiruru (Naha Okinawa, Japan) | Implementation and evaluation of the AES/ADPCM on STP and FPGA with Behavioral Synthesis Yukihito Ishida, Seiya Shibata, Yuki Ando, Shinya Honda, Hiroaki Takada, Masato Edahiro (Nagoya Univ) RECONF2012-14 |
Reconfigurable techniques are attracting attention as an alternative to dedicated hardware of SoC. We have evaluated FP... [more] |
RECONF2012-14 pp.77-82 |
| ITE-MMS, ITE-CE, MRIS [detail] | 2012-01-20 09:30 |
Osaka | A Study of Implementation of Pointing Device in Digital TV Hiroaki Takahashi, Tetsuro Shida, Keiichi Muneishi (Mitsubishi Electric Corp.) |
[more] | ||
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-28 11:20 |
Miyazaki | NewWelCity Miyazaki | An Interrupt Service Handler in Hardware for Ultra-Low Latency Response Naotaka Maruyama (Kernelon Silicon), Tohru Ishihara (Kyoto Univ.), Hiroaki Takada (Nagoya Univ.), Hiroto Yasuura (Kyushu Univ.) VLD2011-57 DC2011-33 |
This paper proposes an interrupt processing in hardware for achieving ultra-low interrupt latency. Several types of mach... [more] | VLD2011-57 DC2011-33 pp.31-36 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-29 09:00 |
Miyazaki | NewWelCity Miyazaki | Synthesis of efficient data fetch mechanism from the high level communication description Masato Minato, Yuki Ando, Seiya Shibata (Nagoya Univ.), Tomoo Kinoshita (Soliton Systems), Shinya Honda, Hiroaki Takada (Nagoya Univ.) VLD2011-67 DC2011-43 |
This paper presents efficient data fetch mechanism for the FIFO-based implementation generated by SystemBuilder, a syste... [more] | VLD2011-67 DC2011-43 pp.91-96 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-29 09:25 |
Miyazaki | NewWelCity Miyazaki | A Runtime Mechanism for Managing of the Scratch-Pad Memory within Real-Time Operating Systems Hideki Takase, Hiroaki Takada (Nagoya Univ.) VLD2011-68 DC2011-44 |
The scratch-pad memory is a suitable on-chip memory for the embedded system in terms of its real-time predictability and... [more] | VLD2011-68 DC2011-44 pp.97-102 |
| RECONF | 2011-09-26 15:30 |
Aichi | Nagoya Univ. | Preemptive Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs - Hardware and Reconfiguration Layers Krzysztof Jozwik, Shinya Honda (Nagoya Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroaki Takada (Nagoya Univ.) RECONF2011-29 |
Preemption techniques for HW (hardware) tasks have been studied in order to improve their responsiveness and to allow ... [more] |
RECONF2011-29 pp.43-48 |
| RECONF | 2011-09-26 16:40 |
Aichi | Nagoya Univ. | [Invited Talk]
Dependability of Automotive Embedded Systems Hiroaki Takada (Nagoya Univ.) RECONF2011-31 |
[more] | RECONF2011-31 p.55 |
| RECONF | 2011-09-27 09:00 |
Aichi | Nagoya Univ. | Case Studies on an FPGA with System-Level Multiprocessor Design Toolset Seiya Shibata, Yuki Ando, Shinya Honda (Nagoya Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroaki Takada (Nagoya Univ.) RECONF2011-32 |
This paper presents a system-level multiprocessor design toolkit: SystemBuilder. SystemBuilder enables system designers... [more] | RECONF2011-32 pp.57-62 |
| USN | 2011-05-20 11:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Energy-saving Sensor Network Using Prediction Memory Takahiro Mimura, Hiroaki Taka, Hideyuki Uehara, Takashi Ohira (Toyohashi Univ. of Tech.) USN2011-2 |
[more] | USN2011-2 pp.5-8 |
| VLD | 2011-03-02 14:25 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | Intra-task Analysis of Worst Case Execution Time and Average Energy Consumption on DEPS Framework Hirotaka Kawashima, Gang Zeng, Noritoshi Atsumi, Tomohiro Tatematsu, Hiroaki Takada (Nagoya Univ.) VLD2010-119 |
In this paper, we show an intra-task average energy consumption(AEC) and worst case execution time(WCET) analysis. The ... [more] | VLD2010-119 pp.19-24 |
| ITE-MMS, MRIS, ITE-CE [detail] | 2011-01-20 15:30 |
Osaka | Shoshin-Kaikan Bldg. | A Study of Efficient Method for Searching Digital Television Program using Genre Information Hiroaki Takahashi, Tetsuro Shida, Hideaki Kosaka (Mitsubishi Electric) |
[more] | |
| AN, MoNA, USN (Joint) |
2011-01-21 16:50 |
Hiroshima | Hiroshima City University | Transmitted Data Size Reduction Method Based on Aggregation Model for Clustering Scheme Hiroaki Taka, Hideyuki Uehara, Takashi Ohira (Toyohashi Univ. of Tech.) USN2010-66 |
In wireless sensor networks, reducing the energy consumption of the whole network is one of the most important research ... [more] | USN2010-66 pp.153-158 |
| AN, USN, SR, RCS (Joint) |
2010-10-29 09:50 |
Osaka | Osaka University | Effect of Aggregation and Reduction of Consumed Energy by Route Division in Chain Structured Sensor Networks Takaaki Mori, Hiroaki Taka, Hideyuki Uehara, Takashi Ohira (Toyohashi Univ. of Tech.) USN2010-35 |
In this paper, we focus on chain structured routings and study the effect of consumed energy reduction when the route de... [more] | USN2010-35 pp.91-96 |
| IT | 2010-07-23 15:20 |
Tokyo | Kogakuin University | On Error Probability of Quantum Logical Gates by using 4 beam Splitter Hiroaki Takao, Hiroki Sato, Noboru Watanabe (Tokyo Univ. of Science) IT2010-32 |
Since logical gates which denotes one of computional principle of present computer is consisted of the different numbe... [more] |
IT2010-32 pp.119-123 |
| IPSJ-SLDM, VLD, CPSY, RECONF [detail] | 2010-01-27 10:25 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Effective Hardware Task Context Switching in Virtex-4 FPGAs Krzysztof Jozwik, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada (Nagoya Univ.) VLD2009-87 CPSY2009-69 RECONF2009-72 |
A unique aspect of flexibility provided by some of the FPGAs such as Xilinx Virtex-4 family is the capability of dynamic... [more] | VLD2009-87 CPSY2009-69 RECONF2009-72 pp.113-118 |
| USN, IPSJ-UBI | 2009-07-16 09:00 |
Kyoto | ATR (Kyoto) | A Proposal of Node Scheduling Method based on Aggregation Model for Wireless Sensor Networks Hiroaki Taka, Hideyuki Uehara, Takashi Ohira (Toyohashi Univ. of Tech.) USN2009-12 |
In wireless sensor networks, reducing energy consumption of the whole network is one of the most important problems. In ... [more] | USN2009-12 pp.1-6 |
[Return to Top Page]