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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 15:35 |
Oita | B-ConPlaza | A Method for Total Length and Length Difference Reduction for Set-Pair Routing Yuta Nakatani, Atsushi Takahashi (Titech)  VLD2014-87 DC2014-41 |
Set pair routing problem in which connection requirements are given between a pair of terminals is a routing problem on... [more] |
VLD2014-87 DC2014-41 pp.111-116 |
| ICD, SDM | 2014-08-04 13:55 |
Hokkaido | Hokkaido Univ., Multimedia Education Bldg. | [Invited Talk]
STT-MRAM Development for Embedded Cache Memory Toshihiro Sugii, Yoshihisa Iba, Masaki Aoki, Hideyuki Noshiro, Koji Tsunoda, Akiyoshi Hatada, Masaaki Nakabayashi, Yuuichi Yamazaki, Atsushi Takahashi, Chikako Yoshida (LEAP) SDM2014-68 ICD2014-37 |
We report the current status of our development of spin-transfer torque magnetic RAMs (STT-MRAMs) and their integration ... [more] | SDM2014-68 ICD2014-37 pp.35-38 |
| ASN | 2014-05-29 14:30 |
Tokyo | Convention Hall, RCAST, The University of Tokyo | [Poster Presentation]
User Initiative Green ICT systems
-- Visualization of a Optimal Energy Mix Building Using IEEE1888 -- Takahide Nakajima (Cimx), Atsushi Takahashi (I-Promotion), Tadashi Makino (Iwatani), Hideya Ochiai, Hiroshi Esaki (Univ. of Tokyo) ASN2014-12 |
Optimal performance for green buildings (modern energy-saving buildings) using, diversified energy source. Vender indepe... [more] | ASN2014-12 pp.43-44 |
| VLD, IPSJ-SLDM | 2014-05-29 11:30 |
Fukuoka | Kitakyushu International Conference Center | LELECUT Triple Patterning Lithography Layout Decomposition using Positive Semidefinite Relaxation Yukihide Kohira (Univ. of Aizu), Tomomi Matsui (Tokyo Tech), Yoko Yokoyama, Chikaaki Kodama (Toshiba), Atsushi Takahashi (Tokyo Tech), Shigeki Nojima, Satoshi Tanaka (Toshiba) VLD2014-6 |
One of the most promising techniques in the 14 nm logic node and beyond is triple patterning lithography (TPL). Recently... [more] | VLD2014-6 pp.27-32 |
| VLD | 2014-03-04 09:15 |
Okinawa | Okinawa Seinen Kaikan | An Enhancement of Length Difference Reduction Algorithm for Set Pair Routing Yusaku Yamamoto, Atsushi Takahashi (Tokyo Inst. of Tech.) VLD2013-142 |
Recent advances in circuit speed force to realize signal propagation delay accurately. In PCB routing design, desired... [more] |
VLD2013-142 pp.49-54 |
| VLD | 2014-03-04 13:50 |
Okinawa | Okinawa Seinen Kaikan | Local Pattern Modification Method for Lithographical ECO in Double Patterning Yutaro Miyabe, Atsushi Takahashi, Tomomi Matsui (Tokyo Inst. of Tech.), Yukihide Kohira (Univ. of Aizu), Yoko Yokoyama (Toshiba) VLD2013-149 |
In advanced semiconductor manufacturing processes, even though a pattern is generated according to a design rule, hot s... [more] |
VLD2013-149 pp.87-92 |
| VLD | 2014-03-04 14:15 |
Okinawa | Okinawa Seinen Kaikan | Self-Aligned Double Patterning-Aware Modified Two-color Grid Routing Takeshi Ihara, Atsushi Takahashi (Tokyo Inst. of Tech.), Chikaaki Kodama (TOSHIBA) VLD2013-150 |
[more] | VLD2013-150 pp.93-98 |
| ICD | 2013-04-11 09:50 |
Ibaraki | Advanced Industrial Science and Technology (AIST) | [Invited Talk]
A Novel MTJ for STT-MRAM with a Dummy Free Layer and Dual Tunnel Junctions Koji Tsunoda, Hideyuki Noshiro, Chikako Yoshida, Yuuichi Yamazaki, Atsushi Takahashi, Yoshihisa Iba, Akiyoshi Hatada, Masaaki Nakabayashi, Takashi Takenaga, Masaki Aoki, Toshihiro Sugii (LEAP) ICD2013-2 |
A novel magnetic tunnel junction (MTJ) for embedded memory applications such as spin transfer torque magneto-resistive r... [more] | ICD2013-2 pp.5-10 |
| VLD | 2013-03-05 14:30 |
Okinawa | Okinawa Seinen Kaikan | A Routing Method Considering Wirelength of Each Net for Single Layer PCB Routing Kyosuke Shinoda, Atsushi Takahashi (Tokyo Inst. of Tech.) VLD2012-149 |
In recent Printed Circuit Board (PCB) design, due to the growth of the density and the increase of the design scale the ... [more] | VLD2012-149 pp.77-82 |
| ICD | 2012-12-17 13:30 |
Tokyo | Tokyo Tech Front | [Invited Talk]
High-performance STT-MRAM and Its Integration for Embedded Application Toshihiro Sugii, Yoshihisa Iba, Masaki Aoki, Hideyuki Noshiro, Koji Tsunoda, Akiyoshi Hatada, Masaaki Nakabayashi, Yuuichi Yamazaki, Atsushi Takahashi, Chikako Yoshida (LESP) ICD2012-90 |
High-performance spin transfer torque MRAM (STT-MRAM) for embedded cache memories was developed, utilizing a top-pinned ... [more] | ICD2012-90 pp.17-20 |
| IE, SIP, ICD, VLD, IPSJ-SLDM [detail] | 2012-10-19 14:55 |
Iwate | Hotel Ruiz | Fast Estimation of Dynamic Delay Distribution Dai Akita, Kenta Ando (Osaka Univ.), Atsushi Takahashi (Tokyo Tech.) VLD2012-55 SIP2012-77 ICD2012-72 IE2012-79 |
As the improvement of digital circuits with fixed latency is about to reach its own limits, it is expected that variable... [more] | VLD2012-55 SIP2012-77 ICD2012-72 IE2012-79 pp.83-88 |
| ICD, SDM | 2012-08-02 15:15 |
Hokkaido | Sapporo Center for Gender Equality, Sapporo, Hokkaido | [Invited Talk]
STT-MRAM Development and Its Integration with BEOL Process for Embedded Applications Toshihiro Sugii, Yoshihisa Iba, Masaki Aoki, Hideyuki Noshiro, Koji Tsunoda, Akiyoshi Hatada, Masaaki Nakabayashi, Yuuichi Yamazaki, Atsushi Takahashi, Chikako Yoshida (LEAP) SDM2012-73 ICD2012-41 |
[more] | SDM2012-73 ICD2012-41 pp.55-58 |
| VLD | 2012-03-07 14:35 |
Oita | B-con Plaza | Performance of the Evaluation of a Variable-Latency-Circuit on FPGA Yuuta Ukon, Kenta Ando, Atsushi Takahashi (Osaka Univ) VLD2011-141 |
The performance of integrated circuits, which are the base of ICT nowaday, is always requested to be improved. In de f... [more] |
VLD2011-141 pp.127-132 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-30 10:05 |
Miyazaki | NewWelCity Miyazaki | A length difference reduction algorithm by using flow in set pair routing problem for single layer PCB routing Yusaku Yamamoto, Atsushi Takahashi (Osaka Univ.) VLD2011-87 DC2011-63 |
Recent advances in circuit speed forces to realize signal propagation delay accurately. In PCB routing design, desire... [more] |
VLD2011-87 DC2011-63 pp.203-208 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-30 10:30 |
Miyazaki | NewWelCity Miyazaki | An Improved Simulated Annealing for 3D Packing with Sequence Triple and Quintuple Representations Yiqiang Sheng (Tokyo Inst. of Tech.), Atsushi Takahashi (Osaka Univ.), Shuichi Ueno (Tokyo Inst. of Tech.) VLD2011-88 DC2011-64 |
The 3D packing for VLSI physical design is facing big challenges to get better solution quality with less computational ... [more] | VLD2011-88 DC2011-64 pp.209-214 |
| VLD | 2011-09-26 14:50 |
Fukushima | University of Aizu | MSA: Mixed Stochastic Algorithm for Placement with Larger Solution Space Yiqiang Sheng (Tokyo Inst. of Tech.), Atsushi Takahashi (Osaka Univ.), Shuichi Ueno (Tokyo Inst. of Tech.) VLD2011-42 |
The optimization techniques for VLSI/PCB placement with larger solution space and more objectives are facing big challen... [more] | VLD2011-42 pp.11-16 |
| VLD | 2011-09-26 15:55 |
Fukushima | University of Aizu | On set pair routing problem Atsushi Takahashi (Osaka Univ.) VLD2011-44 |
In this manuscript, set pair routing problem in which connection requirements are given between a pair of terminal sets ... [more] | VLD2011-44 pp.23-28 |
| MSS, CAS, VLD, SIP | 2011-07-01 14:30 |
Okinawa | Okinawa-Ken-Seinen-Kaikan | Performance Evaluation of Various Configurations of Adder in Error Detection/Correction Circuits Kenta Ando, Atsushi Takahashi (Osaka Univ.) CAS2011-26 VLD2011-33 SIP2011-55 MSS2011-26 |
The performance of a circuit is improved by introducing error detection/correction mechanism which uses the variation of... [more] | CAS2011-26 VLD2011-33 SIP2011-55 MSS2011-26 pp.147-152 |
| VLD | 2011-03-04 10:25 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | CRP : Efficient Topology Modification for Minimum Perturbation Placement Realization Yuki Kouno, Yasuhiro Takashima (Univ. of Kitakyushu), Atsushi Takahashi (Osaka Univ.) VLD2010-138 |
[more] | VLD2010-138 pp.129-134 |
| VLD | 2011-03-04 13:10 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | An evaluation of error detection/correction circuits by gate level simulation Masafumi Inoue (Tokyo Tech.), Yuuta Ukon, Atsushi Takahashi (Osaka Univ.) VLD2010-141 |
In a typical synchronous circuit design, the maximum delay between flip-flops gives a lower bound of the clock period su... [more] | VLD2010-141 pp.147-152 |
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