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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SDM, ICD | 2011-08-26 13:40 |
Toyama | Toyama kenminkaikan | Ultra low noise in-substrate-bitline sense amplifier for 4F2 DRAM array Yoshimitsu Yanagawa, Tomonori Sekiguchi, Akira Kotabe, Kazuo Ono, Riichiro Takemura (Hitachi)  SDM2011-89 ICD2011-57 |
An in-substrate-bitline sense amplifier (SA) with an array-noise-gating (ANG) scheme for stable sensing operation in a 4... [more] | SDM2011-89 ICD2011-57 pp.93-97 |
| SDM, ICD | 2011-08-26 14:05 |
Toyama | Toyama kenminkaikan | Sense Amplifier with Current Control Switch for Small-sized 0.5-V Gigabit-DRAM Arrays Akira Kotabe, Yoshimitsu Yanagawa, Riichiro Takemura, Tomonori Sekiguchi, Kiyoo Itoh (Hitachi) SDM2011-90 ICD2011-58 |
[more] | SDM2011-90 ICD2011-58 pp.99-102 |
| ICD | 2011-04-19 14:00 |
Hyogo | Kobe University Takigawa Memorial Hall | 1-Tbyte/s 1-Gbit Multicore DRAM Architecture using 3-D Integration for High-throughput Computing Kazuo Ono, Yoshimitsu Yanagawa, Akira Kotabe, Tomonori Sekiguchi (Hitachi, CRL) ICD2011-15 |
A novel multicore DRAM architecture with an ultra high bandwidth and a large capacity is proposed for high throughput co... [more] | ICD2011-15 pp.81-86 |
| ICD, SDM | 2010-08-26 13:00 |
Hokkaido | Sapporo Center for Gender Equality | 1-Tbyte/s 1-Gbit 3-D DRAM Architecture for High Throughput Computing Yoshimitsu Yanagawa, Kazuo Ono, Akira Kotabe, Tomonori Sekiguchi (Hitachi) SDM2010-131 ICD2010-46 |
A novel DRAM architecture with an ultra high bandwidth is proposed for high throughput computing. The proposed architect... [more] | SDM2010-131 ICD2010-46 pp.39-44 |
| ICD | 2010-04-22 12:05 |
Kanagawa | Shonan Institute of Tech. | Low-VT CMOS Preamplifier for 0.5-V Gigabit-DRAM Arrays Akira Kotabe, Yoshimitsu Yanagawa, Satoru Akiyama, Tomonori Sekiguchi (Hitachi) ICD2010-6 |
A novel low-VT CMOS preamplifier was developed for low-power and high-speed gigabit DRAM arrays. The sensing time of the... [more] | ICD2010-6 pp.29-33 |
| ICD | 2009-04-13 13:30 |
Miyagi | Daikanso (Matsushima, Miyagi) | [Invited Talk]
Trend in Multi-Gigabit DRAM Technology and Low-Vt Small-Offset Gated Preamplifier for Sub-1-V Arrays Satoru Akiyama, Tomonori Sekiguchi, Riichiro Takemura, Akira Kotabe, Kiyoo Itoh (Hitachi, Ltd.,) ICD2009-2 |
[more] | ICD2009-2 pp.7-12 |
| ICD, SDM | 2005-08-19 13:50 |
Hokkaido | HAKODATE KOKUSAI HOTEL | A 0.4-V High-Speed Long-Retention-Time DRAM Array with 12 F2 Twin Cell Riichiro Takemura, Kiyoo Itoh, Tomonori Sekiguchi, Satoru Akiyama, Satoru Hanzawa (Hitachi), Kazuhiko Kajigaya (ELPIDA), Takayuki Kawahara (Hitachi) |
We propose and evaluate a DRAM cell array with 12-F2 twin cell in terms of speed, retention time, and low-voltage operat... [more] | SDM2005-152 ICD2005-91 pp.55-60 |
| ICD | 2005-04-14 14:30 |
Fukuoka | [Invited Talk]
Statistical Integration In Multigigabit DRAM Design Tomonori Sekiguchi, Satoru Akiyama (Hitachi), Kazuhiko Kajigaya (Elpida), Satoru Hanzawa, Riichiro Takemura, Takayuki Kawahara (Hitachi) |
Concordant memory-array design incorporates device fluctuations statistically into signal-to-noise ratio analysis in DRA... [more] | ICD2005-8 pp.37-42 |
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