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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2014-11-26
09:15		 Oita B-ConPlaza Design of Flip-Flop with Timing Error Tolerance
Taito Suzuki, Youhua Shi, Nozomu Togawa (Waseda Univ.), Kimiyoshi Usami (SIT), Masao Yanagisawa (Waseda Univ.) VLD2014-79 DC2014-33		 Under the influence of the miniaturization of the integrated circuit, the variation of the operation condition of the ci... [more] VLD2014-79 DC2014-33
pp.45-50
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