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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 6 of 6  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM 2021-11-11
11:00		 Online Online [Invited Talk] Non-Normal Model Parameter Generation for Variation-Aware Circuit Simulation
Takashi Sato, Hiroki Tsukamoto, Song Bian (Kyoto Univ.), Michihiro Shintani (NAIST) SDM2021-54		  [more] SDM2021-54
pp.7-12
HWS, VLD [detail] 2020-03-05
14:55		 Okinawa Okinawa Ken Seinen Kaikan
(Cancelled but technical report was issued)		 [Memorial Lecture] A Tuning-Free Hardware Reservoir Based on MOSFET Crossbar Array for Practical Echo State Network Implementation
Yuki Kume, Song Bian, Takashi Sato (Kyoto Univ.) VLD2019-118 HWS2019-91		 Echo state network (ESN) is a class of recurrent neural network, and is known for drastically reducing the training time... [more] VLD2019-118 HWS2019-91
pp.139-144
HWS, VLD [detail] 2020-03-06
16:50		 Okinawa Okinawa Ken Seinen Kaikan
(Cancelled but technical report was issued)		 Performance Evaluation of Echo State Networks with Hardware Reservoirs
Yuki Kume, Song Bian, Kenta Nagura, Takashi Sato (Kyoto Univ.) VLD2019-136 HWS2019-109		 Echo state Network (ESN), a class of recurrent neural network, is characteristic in its use of a reservoir having random... [more] VLD2019-136 HWS2019-109
pp.245-250
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]		 2018-12-07
09:50		 Hiroshima Satellite Campus Hiroshima A study on estimating the degradation of critical path delay using replica sensors
Kunihiro Oshima, Son Bian, Masayuki Hiromoto, Takashi Sato (Kyoto Univ.) VLD2018-67 DC2018-53		 In this paper, we propose a novel method to estimate the aging-induced timing degradation of logic circuits. In the prop... [more] VLD2018-67 DC2018-53
pp.195-200
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]		 2017-11-07
09:50		 Kumamoto Kumamoto-Kenminkouryukan Parea A PUF Based on the Instantaneous Response of Ring Oscillator Determined by the Convergence Time of Bistable Ring Oscillator Circuit
Yuki Tanaka, Song Bian, Masayuki Hiromoto, Takashi Sato (Kyoto Univ.) VLD2017-40 DC2017-46		 Studies on physical unclonable function (PUF) have been actively conducted as one of the countermeasures against counter... [more] VLD2017-40 DC2017-46
pp.79-84
VLD 2015-03-03
08:50		 Okinawa Okinawa Seinen Kaikan A Processor-Level NBTI Mitigation Technique of Applying Anti-Aging Gate Control through Instruction Set Architecture
Song Bian, Michihiro Shintani (Kyoto Univ.), Zheng Wang (RWTH Aachen Univ.), Masayuki Hiromoto (Kyoto Univ.), Anupam Chattopadhyay (Nanyang Tech. Univ.), Takashi Sato (Kyoto Univ.) VLD2014-161		  [more] VLD2014-161
pp.49-54
 Results 1 - 6 of 6  /   
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