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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD, IPSJ-ARC, IPSJ-EMB | 2009-01-13 10:00 |
Osaka | Shoushin Kaikan | A 820 Mb/s Baseband Processor LSI based on LDPC Coded OFDM for UWB systems Shinsuke Ushiki, Koichi Nakamura, Kazunori Shimizu, Qi Wang, Yuta Abe, Satoshi Goto, Takeshi Ikenaga (Waseda Univ.)  ICD2008-130 |
This paper presents a high-throughput and highly-reliable baseband processor LSI based on LDPC coding OFDM UWB. This LSI... [more] | ICD2008-130 pp.7-12 |
| VLD, ICD | 2008-03-07 10:45 |
Okinawa | TiRuRu | A High-Throughput Architectures for LDPC Coded OFDM Baseband Processor Shinsuke Ushiki, Koichi Nakamura, Kazunori Shimizu, Qi Wang, Yuta Abe, Satoshi Goto, Takeshi Ikenaga (Waseda Univ.) VLD2007-159 ICD2007-182 |
It's research target more important that combined OFDM modulation with LDPC codes in digital wireless communication syst... [more] | VLD2007-159 ICD2007-182 pp.19-24 |
| VLD, ICD | 2008-03-07 11:10 |
Okinawa | TiRuRu | Design of High-rate Irregular LDPC Decoder based on Accelerated Message-passing Schedule Yuta Abe, Naoki Tajima, Xing Li, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto (Waseda Univ.) VLD2007-160 ICD2007-183 |
In this paper, We Design of High Throughput Multi-rate Irregular LDPC Decoder based on Accelerated Message-Passing Sched... [more] | VLD2007-160 ICD2007-183 pp.25-30 |
| VLD, ICD | 2008-03-07 11:35 |
Okinawa | TiRuRu | Low Power Design of Accelerated Message-Passing LDPC Decoder for Long Codes Naoki Tajima, Yuta Abe, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto (Waseda Univ.) |
LDPC codes that quality is very close to Shannon limit become more important with the developments of radio communicatio... [more] | |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-22 10:30 |
Fukuoka | Kitakyushu International Conference Center | A Multi-Rate Compatible Irregular LDPC Decoder Enhancing Column Operation Parallelism Yuta Imai, Kazunori Shimizu, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) RECONF2007-46 |
Recently, needs for downloading digital contents via wireless network have been dramatically increasing as high-function... [more] | RECONF2007-46 pp.19-24 |
| ICD, IPSJ-ARC | 2007-05-31 17:15 |
Kanagawa | A high-throughput, low-power FFT circuits for OFDM based wireless communication systems Shinsuke Ushiki, Kazunori Shimizu, Koichi Nakamura, Satoshi Goto, Takeshi Ikenaga (Waseda Univ.) ICD2007-26 |
OFDM attracts attention in digital wireless communication systems. In the FFT circuit which is main processing of digita... [more] | ICD2007-26 pp.55-60 |
|
| VLD, IPSJ-SLDM | 2007-05-11 11:20 |
Kyoto | Kyodai Kaikan | An SIMD MSD Multiplier based on variable GF($2^m$) for Elliptic Curve Cryptosystem Ryuta Nara, Kazunori Shimizu, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2007-11 |
Originally elliptic curve cryptosystem (ECC) hardware are often required to operate variable key length. Digit-serial mu... [more] | VLD2007-11 pp.25-29 |
| ICD, VLD | 2007-03-07 13:40 |
Okinawa | Mielparque Okinawa | Partially-parallel decoder based on high-efficiency message-passing schedule for irregular LDPC code Xing Li, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto (Waseda Univ.) |
In this paper we propose an efficient Message-Passing schedule which is suitable for irregular LDPC decoder. For the dec... [more] | VLD2006-108 ICD2006-199 pp.13-18 |
| VLD, CPSY, RECONF, IPSJ-SLDM | 2007-01-17 15:15 |
Tokyo | Keio Univ. Hiyoshi Campus | GF(2^m) Digit-Serial Multiplier for Elliptic Curve Cryptosystem Ryuta Nara, Shunitsu Kohara, Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Masao Yanagisawa, Satoshi Goto, Tatsuo Ohtsuki (Waseda Univ) |
[more] | VLD2006-89 CPSY2006-60 RECONF2006-60 pp.25-30 |
| ICD, ITE-CE | 2006-12-15 15:10 |
Hiroshima | A 0.3mW 1.4mm2 Motion Estimation Processor LSI for Mobile Video Application Seiichiro Hiratsuka (Fukuoka IST), Kazunori Shimizu, Satoshi Goto, Takeshi Ikenaga (Waseda Univ.) |
[more] | ICD2006-168 pp.143-148 |
|
| RECONF, CPSY, VLD, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2006-11-29 16:45 |
Fukuoka | Kitakyushu International Conference Center | An Implementation of dynamically reconfigurable multi-rate compatible LDPC decoder Yuta Imai, Kazunori Shimizu, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) |
[more] | RECONF2006-43 pp.35-40 |
| ICD, ITE-CE | 2006-01-27 14:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | High-Throughput LDPC Decoder Based on Memory-Reduction Method Tatsuyuki Ishikawa, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto (Waseda Univ.) |
In this paper, we propose a high-throughput partially-parallel LDPC decoder for long code-length. The decoder achieves... [more] |
ICD2005-220 pp.29-34 |
| CAS, SIP, VLD | 2005-06-28 14:15 |
Miyagi | Tohoku University | A Memory-Reduction Method for Partially-Parallel LDPC Decoder Based on Min-Sum Algorithm Tatsuyuki Ishikawa, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto (Waseda Univ.) |
In this paper, we propose a memory-reduction method for partially-parallel LDPC decoder based on min-sum algorithm. We ... [more] | CAS2005-22 VLD2005-33 SIP2005-46 pp.43-48 |
| VLD, ICD | 2005-03-10 - 2005-03-11 |
Okinawa | Mielparque Okinawa | Implementation and Evaluation of Partial-Parallel LDPC Decoder Improving Blief Propagation based on Sum-Product Algorithm Kazunori Shimizu, Tatsuyuki Ishikawa (Waseda Univ.), Nozomu Togawa (The Univ. of Kitakyushu), Takeshi Ikenaga, Satoshi Goto (Waseda Univ.) |
[more] | VLD2004-149 ICD2004-245 pp.73-78 |
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