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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD | 2024-04-11 13:50 |
Kanagawa | (Primary: On-site, Secondary: Online) |
[Invited Lecture]
A 22 nm 10.8 Mb Embedded STT MRAM Macro Achieving over 200 MHz Random Read Access and a 10.4 MB/s Write Throughput for High End MCUs Masayuki Izuna, Tomoya Ogawa, Ken Matsubara, Yasuhiko Taito, Tomoya Saito, Koichi Takeda, Yoshinobu Kaneda, Takahiro Shimoi, Hidenori Mitani, Takashi Ito, Takashi Kono (Renesas Electronics)  ICD2024-6 |
(To be available after the conference date) [more] | ICD2024-6 pp.18-19 |
| ICD | 2023-04-10 11:00 |
Kanagawa | (Primary: On-site, Secondary: Online) |
[Invited Lecture]
A 22nm 32Mb Embedded STT-MRAM Macro Achieving 5.9ns Random Read Access and 5.8MB/s Write Throughput at up to Tj of 150 °C Takahiro Shimoi, Ken Matsubara, Tomoya Saito, Tomoya Ogawa, Yasuhiko Taito, Yoshinobu Kaneda, Masayuki Izuna, Koichi Takeda, Hidenori Mitani, Takashi Ito, Takashi Kono (Renesas Electronics) ICD2023-2 |
This paper presents a high-precision sense amplifier and a fast write throughput technique of a 32Mb embedded STT-MRAM m... [more] | ICD2023-2 p.7 |
| SDM | 2022-01-31 13:15 |
Online | Online | [Invited Talk]
**** Tomoya Saito, Takashi Ito, Yasuhiko Taito, Kenichiro Sonoda, Genta Watanabe, Ken Matsubara, Akihiko Kanda, Takahiro Shimoi, Koichi Takeda, Takashi Kono (Renesas) SDM2021-68 |
We present the low energy write techniques and measurement results of a 20Mb embedded STT-MRAM test chip in 16nm FinFET ... [more] | SDM2021-68 pp.1-4 |
| SDM, ICD | 2015-08-25 09:30 |
Kumamoto | Kumamoto City | [Invited Talk]
Low-Power Embedded ReRAM Technology for IoT Applications Makoto Ueki, Akira Tanabe, Hiroshi Sunamura, Mitsuru Narihiro, Kazuya Uejima, Koji Masuzaki, Naoya Furutake, Akira Mitsuiki, Koichi Takeda, Takashi Hase, Yoshihiro Hayashi (Renesas Electronics) SDM2015-65 ICD2015-34 |
A low-power 2Mb ReRAM macro was developed in 90 nm CMOS platform, demonstrating lower power data-writing (x1/7-x1/10) an... [more] | SDM2015-65 ICD2015-34 pp.41-46 |
| SCE | 2015-01-22 09:50 |
Tokyo | Kikaishinkou-kaikan | Towards precise current-multiplier based on the quantum current-mirror effect Kouichi Takeda, Kenji Miyawaki, Srinivas Gandrothula, Chihiro Ishida, Ayano Hagiwara, Yoshinao Mizugaki, Hiroshi Shimada (UEC) SCE2014-49 |
In the system of capacitively coupled linear arrays of small Josephson junctions, a current duplication phenomenon with ... [more] | SCE2014-49 pp.1-6 |
| SDM | 2012-03-05 10:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Basic Performance of a Logic-IP Compatible eDRAM with Cylinder Capacitors in Low-k/Cu BEOL Layers Ippei Kume, Naoya Inoue, Ken'ichiro Hijioka, Jun Kawahara, Koichi Takeda, Naoya Furutake, Hiroki Shirai, Kenya Kazama, Shin'ichi Kuwabara, Msasatoshi Watarai, Takashi Sakoh, Toshifumi Takahashi, Takashi Ogura, Toshiji Taiji, Yoshiko Kasama (Renesas Electronics) SDM2011-177 |
We have confirmed the basic performance of a Logic-IP compatible (LIC) eDRAM with cylinder capacitors in the low-k/Cu BE... [more] | SDM2011-177 pp.7-11 |
| ICD | 2011-04-19 10:20 |
Hyogo | Kobe University Takigawa Memorial Hall | Multi-step Word-line Control Technology in Hierarchical Cell Architecture for Scaled-down High-density SRAMs Koichi Takeda, Toshio Saito, Shinobu Asayama, Yoshiharu Aimoto, Hiroyuki Kobatake, Shinya Ito, Toshifumi Takahashi, Kiyoshi Takeuchi, Masahiro Nomura, Yoshihiro Hayashi (Renesas Electronics) ICD2011-10 |
[more] | ICD2011-10 pp.55-58 |
| ICD | 2006-04-14 11:40 |
Oita | Oita University | Redefinition of Write Margin for Next-Generation SRAMs and Write-Margin Monitoring Circuits Koichi Takeda, Hidetoshi Ikeda, Yasuhiko Hagihara, Masahiro Nomura (NEC), Hiroyuki Kobatake (NECEL) |
[more] | ICD2006-16 pp.85-90 |
| ICD, SDM | 2005-08-18 14:55 |
Hokkaido | HAKODATE KOKUSAI HOTEL | Monitoring Scheme for Minimizing Power Consumption by Means of Supply and Threshold Voltage Control in Active and Standby Modes Yoshifumi Ikenaga, Masahiro Nomura, Koichi Takeda, Yoetsu Nakazawa (NEC), Yoshiharu Aimoto (NECEL), Yasuhiko Hagihara (NEC) |
(Advance abstract in Japanese is available) [more] | SDM2005-139 ICD2005-78 pp.67-72 |
| ICD | 2005-04-14 09:00 |
Fukuoka | A Read-Static-Noise-Margin-Free SRAM cell for low-Vdd and High-speed applications Koichi Takeda, Yasuhiko Hagihara (NEC), Yoshiharu Aimoto (NECEL), Masahiro Nomura, Yoetsu Nakazawa (NEC), Toshio Ishii, Hiroyuki Kobatake (NECEL) |
A read-static-noise-margin-free SRAM cell consists of seven transistors, several of which are low-Vt NMOS transistors us... [more] | ICD2005-1 pp.1-6 |
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