Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
RECONF |
2023-08-04 13:40 |
Hokkaido |
Hakodate Arena (Primary: On-site, Secondary: Online) |
[Invited Talk]
Tightly-coupled microservice execution platform Ryuichi Sakamoto (Tokyo Tech) |
[more] |
|
RCS |
2021-06-23 16:10 |
Online |
Online |
Proof of concept of Normally-off type local 5G base station Kazutami Arimoto (Okaya.a Prefectural Univ.), Hiroshi Nakamura, Ryuichi Sakamoto, Yuta Suzuki (Univ. of Tokyo), Hideharu Takebe (poco-apoco Networks), Noriaki Yoshikawa, Kensaku Kinosita (Cyber Creative Institute), Tomoyuki Ohya (DOCOMO Technology) RCS2021-44 |
Using open software and software defined radio, we developed a proof-of-concept facility (PoC) for a normally-off local ... [more] |
RCS2021-44 pp.91-96 |
CPSY, DC, IPSJ-ARC [detail] |
2020-07-30 16:15 |
Online |
Online |
Preliminary examination of normally-off power management for local 5G base station Yuta Suzuki, Ryuichi Sakamoto, Hiroshi Nakamura (UTokyo) CPSY2020-5 DC2020-5 |
It is necessary to reduce power consumption of base stations (BSs) in local 5G network. This article proposes applying n... [more] |
CPSY2020-5 DC2020-5 pp.29-35 |
SR, NS, SeMI, RCC, RCS (Joint) |
2020-07-09 13:00 |
Online |
Online |
Concept of Normally-off type local 5G base station with energy matching AI Kazutami Arimoto (Okayama Prefectual Univ.), Hiroshi Nakamura, Ryuichi Sakamoto, Yuta Suzuki (Univ. of Tokyo), Hideharu Takebe (poco-apoco Networks Co. Ltd), Noriaki Yoshikawa, Kensaku Kinosita (Cyber Creative Institute Co., Ltd.) RCC2020-4 NS2020-33 RCS2020-67 SR2020-12 SeMI2020-4 |
[more] |
RCC2020-4 NS2020-33 RCS2020-67 SR2020-12 SeMI2020-4 pp.13-18(RCC), pp.13-18(NS), pp.55-60(RCS), pp.19-24(SR), pp.7-12(SeMI) |
VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2019-11-15 15:45 |
Ehime |
Ehime Prefecture Gender Equality Center |
Ryohei Tomura, Takuya Kojima, Hideharu Amano (Keio Univ.), Ryuichi Sakamoto, Masaaki Kondo (UTokyo) CPSY2019-49 |
SNACC (Scalable Neuro Accelerator Core with Cubic integration) is an accelerator for deep neural network, which can impr... [more] |
CPSY2019-49 pp.65-70 |
CPSY, DC, IPSJ-ARC [detail] |
2019-07-24 10:45 |
Hokkaido |
Kitami Civic Hall |
CPSY2019-17 DC2019-17 |
(To be available after the conference date) [more] |
CPSY2019-17 DC2019-17 pp.1-6 |
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] |
2017-03-10 14:30 |
Okinawa |
Kumejima Island |
Compiler Toolchain of Deep Learning Accelerator with Wireless 3D Stacked Chips Tetsui Ohkubo, Takuya Kojima, Hideharu Amano (Keio Univ.), Ryo Takata, Jun Ishii, Ryuichi Sakamoto, Masaaki Kondo, Hiroshi Nakamura (Tokyo Univ.) CPSY2016-155 DC2016-101 |
[more] |
CPSY2016-155 DC2016-101 pp.357-362 |
CPSY, DC (Joint) |
2014-07-30 18:15 |
Niigata |
Toki Messe, Niigata |
Design of OpenCL Library and Execution Dispatcher for Embedded Accelerator Ryuichi Sakamoto, Mikiko Sato (Tokyo Univ. of Agriculture and Tech. (TUAT)), Hideharu Amano, Tadahiro Kuroda (Keio Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech.), Hiroshi Nakamura (Univ. of Tokyo), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech. (TUAT)) CPSY2014-46 |
Recently, an embedded processor for use in smartphones and other devices is equipped with some power-efficient accelerat... [more] |
CPSY2014-46 pp.215-220 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 10:25 |
Kagoshima |
|
Development of a fine-grain power-gated CPU "Geyser-3" and adaptive power-off control to the temperature Kimiyoshi Usami, Masaru Kudo, Kensaku Matsunaga, Tsubasa Kosaka, Yoshihiro Tsurui (Shibaura Inst. of Tech.), Weihan Wang, Hideharu Amano (Keio Univ), Ryuichi Sakamoto, Mitaro Namiki (Tokyo Univ of Agriculture and Tech), Masaaki Kondo (Univ of Elec-Comm), Hiroshi Nakamura (Univ of Tokyo) VLD2013-80 DC2013-46 |
[more] |
VLD2013-80 DC2013-46 pp.135-140 |
CPSY |
2013-10-03 11:35 |
Chiba |
Makuhari Messe |
A Chip Evaluation of Cube-1: A multi-core processor with 3D TCI Hideharu Amano, Yusuke Koizumi (Keio Univ.), Noriyuki Miura (Kobe Univ.), Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda (Keio Univ.), Ryuichi Sakamoto, Mitaro Namiki (Tokyo Agri. and Tech.), Kimiyoshi Usami, Masaaki Kondo (Univ. of Elect. Comm.), Hiroshi Nakamura (Univ. of Tokyo) CPSY2013-33 |
[more] |
CPSY2013-33 pp.13-18 |
CPSY, VLD, RECONF, IPSJ-SLDM [detail] |
2013-01-16 16:00 |
Kanagawa |
|
Break Even Time Evaluation of Run-Time Power Gating Control by On-chip Leakage Monitor Kensaku Matsunaga, Masaru Kudo (SIT), Yuya Ohta, Nao Konishi (SIT), Hideharu Amano (KU), Ryuichi Sakamoto, Mitaro Namiki (TUAT), Kimiyoshi Usami (SIT) VLD2012-118 CPSY2012-67 RECONF2012-72 |
Run-time Power Gating (RTPG) reduces leakage energy by turning off a power switch(PS) for idle periods of a circuit duri... [more] |
VLD2012-118 CPSY2012-67 RECONF2012-72 pp.63-68 |
RECONF |
2012-05-29 17:35 |
Okinawa |
Tiruru (Naha Okinawa, Japan) |
Development of Application for Heterogeneous Multi-Core Processor Yusuke Koizumi, Eiichi Sasaki, Hideharu Amano (Keio Univ.), Ryuichi Sakamoto, Mitaro Namiki (Tkyo Univ. of Agri. and Tech.) RECONF2012-16 |
This paper describes the application development on a heterogeneous multi-core processor that consists of a CPU and acce... [more] |
RECONF2012-16 pp.89-94 |
DC, CPSY (Joint) |
2011-07-29 09:25 |
Kagoshima |
|
3-D Stacked Architecture using Inductinve Coupling Eiichi Sasaki, Daisuke Sasaki, Hiroki Matsutani, Hideharu Amano, Yasuhiro Take, Tadahiro Kuroda (Keio Univ.), Ryuichi Sakamoto, Mitaro Namiki (TAT) CPSY2011-10 |
Cube-1: a low power heterogeneus 3-D stacked architecture using an inductive-coupling
is proposed.
A low power MIPS R3... [more] |
CPSY2011-10 pp.7-12 |
IPSJ-SLDM, VLD, CPSY, RECONF [detail] |
2010-01-27 10:50 |
Kanagawa |
Keio Univ (Hiyoshi Campus) |
Hardware Acceleration in a Scalable FPGA System Hironori Nakajo, Ryuichi Sakamoto (Tokyo Univ. of Agr and Tech.) VLD2009-88 CPSY2009-70 RECONF2009-73 |
Currently, FPGAs are utilized for hardware experiments or practices in many educational institutes.
In a field of high ... [more] |
VLD2009-88 CPSY2009-70 RECONF2009-73 pp.119-124 |
IPSJ-SLDM, VLD, CPSY, RECONF [detail] |
2010-01-27 11:15 |
Kanagawa |
Keio Univ (Hiyoshi Campus) |
Expansion of Hardware in a Scalable FPGA System Hironori Nakajo (Tokyo Univ. of Agr and Tech.), Takefumi Miyoshi (Tokyo Inst. of Tech.), Satoshi Funada (e-trees.Japan, Inc), Ryuichi Sakamoto (Tokyo Univ. of Agr and Tech.) VLD2009-89 CPSY2009-71 RECONF2009-74 |
Currently, in a field of high performance computing, some FPGAs are utilized to accelerate processing against some forma... [more] |
VLD2009-89 CPSY2009-71 RECONF2009-74 pp.125-130 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-03 14:45 |
Kochi |
Kochi City Culture-Plaza |
Protocol for Expansion of Hardware in a Scalable FPGA System Hironori Nakajo, Ryuichi Sakamoto, Shinobu Miwa (TUAT) |
In this presentation, we have proposed a mechanism to expand hardware in the Scalable FPGA system which has been current... [more] |
|