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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
ICD |
2009-04-13 12:40 |
Miyagi |
Daikanso (Matsushima, Miyagi) |
[Invited Talk]
A 1.6GB/s DDR2 128Mb Chain FeRAM with Scalable Octal Bitline and Sensing Schemes Hidehiro Shiga, Daisaburo Takashima, Shinichiro Shiratake, Katsuhiko Hoya, Tadashi Miyakawa, Ryu Ogiwara, Ryo Fukuda, Ryosuke Takizawa, Kosuke Hatsuda, Fumiyoshi Matsuoka, Yasushi Nagadomi, Daisuke Hashimoto, Hisaaki Nishimura, Takeshi Hioka, Sumiko Dohmae (Toshiba Corp.) ICD2009-1 |
Ferroelectric RAMs (FeRAMs) are expected to be the next generation semiconductor memory for their fast access speed (com... [more] |
ICD2009-1 pp.1-6 |
ICD |
2006-04-13 11:35 |
Oita |
Oita University |
Technology development of 128Mb-FBC(Floating Body Cell) Memory by 90nm node CMOS process Hiroomi Nakajima, Yoshihiro Minami, Tomoaki Shino (SoC Center, Toshiba), Atsushi Sakamoto (TJ), Tomoki Higashi (TOSMEC), Naoki Kusunoki, Katsuyuki Fujita, Kosuke Hatsuda, Takashi Ohsawa, Nobutoshi Aoki, Hiroyoshi Tanimoto, Mutsuo Morikado, Kazumi Inoh, Takeshi Hamamoto, Akihiro Nitayama (SoC Center, Toshiba) |
A 128Mb SOI DRAM with FBC (Floating Body Cell) has been successfully developed for the first time. In order to realize f... [more] |
ICD2006-5 pp.25-30 |
SIP, ICD, IE, IPSJ-SLDM |
2005-10-20 16:50 |
Miyagi |
Ichinobo, Sakunami-Spa |
A 333MHz Random Cycle DRAM Using the Floating Body Cell Kosuke Hatsuda, Katsuyuki Fujita, Takashi Ohsawa (Toshiba Corp.) |
[more] |
SIP2005-114 ICD2005-133 IE2005-78 pp.113-118 |
ICD |
2005-04-14 11:40 |
Fukuoka |
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A 128Mb DRAM Using a 1T Gain Cell(FBC) on SOI Takashi Ohsawa, Katsuyuki Fujita, Kosuke Hatsuda (Toshiba), Tomoki Higashi (Toshiba Microelectronics), Mutsuo Morikado, Yoshihiro Minami, Tomoaki Shino, Hiroomi Nakajima, Kazumi Inoh, Takeshi Hamamoto, Shigeyoshi Watanabe (Toshiba) |
We report on a 128Mbit DRAM design using the capacitor-less DRAM cell or the floating body cell(FBC) on SOI. The cell of... [more] |
ICD2005-5 pp.23-28 |
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