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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD, IPSJ-ARC, IPSJ-EMB | 2010-01-29 13:25 |
Tokyo | T.B.D. | Developing an Architecture for a Single-Flux Quantum Based Reconfigurable Accelerator Farhad Mehdipour (Kyushu Univ.), Hiroaki Honda (ISIT), Hiroshi Kataoka, Koji Inoue, Kazuaki Murakami (Kyushu Univ.)  ICD2009-111 |
As a solution to gain high performance computation, a large scale reconfigurable data-path (LSRDP) processor is introdu... [more] |
ICD2009-111 pp.99-104 |
| ICD, IPSJ-ARC, IPSJ-EMB | 2009-01-14 15:30 |
Osaka | Shoushin Kaikan | Predicting Cache Miss Rates via Simulation Results Reuse Takatsugu Ono, Koji Inoue, Kazuaki Murakami (Kyushu Univ.), Koji Kai (Panasonic) ICD2008-146 |
[more] | ICD2008-146 pp.99-104 |
| CPSY | 2008-10-31 15:45 |
Hiroshima | Hiroshima City Univ. | Performance Evaluation of a Large Scale Reconfigurable Data-Path Utilized for Scientific Application Hiroshi Kataoka (Kyushu Univ.), Hiroaki Honda (ISIT), Farhad Mehdipour, Koji Inoue, Kazuaki Murakami (Kyushu Univ.) CPSY2008-35 |
Recently, Large Scale Reconfigurable Data Path (LSRDP) processor has been proposed for the reduction of required memor... [more] |
CPSY2008-35 pp.35-40 |
| ICD, IPSJ-ARC | 2008-05-14 10:30 |
Tokyo | PSI-SIM: Performance Prediction for Peta-Scale Supercomputers with Thousands of Multi-core Processors Koji Inoue (Kyushu Univ.), Ryutaro Susukita (IST), Hisashige Ando, Shigeru Ishizuki, Hidemi Komatsu (Fujitsu), Yuichi Inadomi, Hiroaki Honda (Kyushu Univ.), Shuji Yamamura (Fujitsu), Hidetomo Shibamura (ISIT), Yunqing Yu, Mutsumi Aoyagi (Kyushu Univ.), Yasunori Kimura (Fujitsu), Kazuaki Murakami (Kyushu Univ.) |
This paper proposes a novel approach to predict the performance of peta-scale supercomputers. It is not easy to accurate... [more] | ICD2008-27 pp.51-56 |
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| ICD, IPSJ-ARC | 2008-05-14 14:15 |
Tokyo | Performance Balancing: An Efficient Helper-Thread Execution on CMPs Kenichi Imazato, Naoto Fukumoto, Koji Inoue, Kazuaki Murakami (Kyushu Univ.) |
Conventional CMPs attempt to exploit the thread-level parallelism (TLP) by using all of the cores integrated in a chip.... [more] |
ICD2008-31 pp.75-80 |
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| ICD, IPSJ-ARC | 2008-05-14 14:45 |
Tokyo | Adaptive Management of Parallelism on Transactional Memories Susumu Takeda, Keita Shimasaki, Koji Inoue, Kazuaki Murakami (kyushu Univ.) |
[more] | ICD2008-32 pp.81-86 |
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| ICD, IPSJ-ARC | 2008-05-14 17:00 |
Tokyo | Performance Balancing: An Implementation of Efficient On-chip Memory Hierarchy on Cell/B.E. Tetsuo Hayashi, Naoto Fukumoto, Kenichi Imazato, Koji Inoue, Kazuaki Murakami (Kyushu Univ.) |
We have proposed the concept of Performance Balancing to improve the CMP performance. This approach attempts to exploit ... [more] | ICD2008-36 pp.105-110 |
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| ICD, IPSJ-ARC | 2008-05-14 17:30 |
Tokyo | Quantitative Analysis of Memory Workload on Chip-Multiprocessors Mitsuaki Yamaguchi, Koji Inoue, Kazuaki Murakami (Kyushu Univ.) |
Integrating multiple processor cores into a single chip, or chip-multiprocessors (CMPs) is one of the most promising ap... [more] |
ICD2008-37 pp.111-116 |
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| RECONF, CPSY, VLD, IPSJ-SLDM | 2008-01-17 16:25 |
Kanagawa | Hiyoshi Campus, Keio University | A Hybrid Design Space Exploration Approach for a Coarse-Grained Reconfigurable Accelerator Farhad Mehdipour (Kyushu Univ.), Hamid Noori (ISIT), Hiroaki Honda, Koji Inoue, Kazuaki Murakami (Kyushu Univ.) VLD2007-133 CPSY2007-76 RECONF2007-79 |
Multitude parameters involved in the design process of a reconfigurable accelerator which is exploited in embedded syste... [more] | VLD2007-133 CPSY2007-76 RECONF2007-79 pp.89-94 |
| CPSY | 2007-10-26 10:20 |
Kumamoto | Kumamoto University | PSI-NSIM: A Parallel Interconnection Network Simulator for Performance Analysis of Large-scale Parallel Systems Hidetomo Shibamura (ISIT), Ryutaro Susukita (Fukuoka IST), Hiroaki Honda, Yuichi Inadomi, Yunqing Yu, Koji Inoue, Mutsumi Aoyagi (Kyushu Univ.) CPSY2007-32 |
This paper presents an interconnection network simulator, PSI-NSIM, toward designing and performance analysis of large-s... [more] | CPSY2007-32 pp.45-50 |
| SIP, ICD, IE, IPSJ-SLDM (Joint) [detail] |
2007-10-26 13:15 |
Fukushima | Aidu-Higasiyama-Onsen Kuturogijuku | [Invited Talk]
- Koji Inoue (Kyushu Univ.) |
[more] | |
| ICD, IPSJ-ARC | 2007-05-31 11:30 |
Kanagawa | The Potential of Temperature-Aware Configurable Cache on Energy Reduction Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki Murakami (Kyushu Univ.) |
Active power used to be the primary contributor to total power dissipation of CMOS designs, but with the technology sca... [more] |
ICD2007-19 pp.13-18 |
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| ICD, IPSJ-ARC | 2007-05-31 13:15 |
Kanagawa | Effect of Data Prefetching on Chip MultiProcessor Naoto Fukumoto, Tomonobu Mihara, Koji Inoue, Kazuaki Murakami (Kyushu Univ.) |
Chip MultiProcessors (or CMPs) can achieve higher performance by means of exploiting thread level parallelism. Increasin... [more] | ICD2007-20 pp.19-24 |
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| ICD, IPSJ-ARC | 2007-06-01 10:30 |
Kanagawa | Fast, Accurate Cache Simulation Takatsugu Ono, Koji Inoue, Kazuaki Murakami (Kyushu Univ.) |
[more] | ICD2007-27 pp.61-66 |
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| ICD, IPSJ-ARC | 2007-06-01 17:15 |
Kanagawa | On-chip Network Architecture for Large Scale Reconfigurable Datapath Keita Shimasaki, Takaaki Nagano, Hiroaki Honda, Farhad Mehdipour, Koji Inoue, Kazuaki Murakami (Kyushu Univ.) ICD2007-36 |
[more] | ICD2007-36 pp.115-120 |
|
| RECONF | 2007-05-18 10:40 |
Ishikawa | Kanazawa Bunka Hall | A Study of the Dynamic Reconfigurable Processor Vulcan2 and Its Development Tool ISAcc Tetsuo Hiraki, Shingo Kadouchi, Yosuke Yamazaki (Kyushu Univ.), Takayuki Kando, Lovic Gauthier, Victor Goulart Mauro Ferreira (FLEETS), Antoine Trouve (ISIT), Koji Inoue, Kazuaki Murakami (Kyushu Univ.) RECONF2007-13 |
Application specific extensions of a processor provide higher performance. In this paper, the authors propose``Vulcan2''... [more] | RECONF2007-13 pp.73-78 |
| SCE | 2007-01-26 14:15 |
Tokyo | SRL | [Invited Talk]
A processor with a large-scale reconfigurable data-path using rapid single flux quantum circuits Naofumi Takagi (Nagoya Univ.), Kazuaki Murakami (Kyushu Univ.), Akira Fujimaki (Nagoya Univ.), Nobuyuki Yoshikawa (Yokohama National Univ.), Koji Inoue, Hiroaki Honda (Kyushu Univ.) |
A processor with a large-scale reconfigurable data-path using rapid single flux quantum circuits is proposed for a 10TFL... [more] | SCE2006-36 pp.37-40 |
| ICD, IPSJ-ARC | 2006-06-08 10:00 |
Kanagawa | A Case for Hot-Path-based Branch Prediction Kosuke Tsuiji, Koji Inoue, Kazuaki Murakami (Kyushu Univ.) |
[more] | ICD2006-40 pp.1-6 |
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| ICD, IPSJ-ARC | 2006-06-08 10:30 |
Kanagawa | A Low-Power, Reliable Datapath by Reusing Execution Results Yosuke Hashiguchi, Koji Inoue, Kazuaki Murakami (Kyushu Univ) |
[more] | ICD2006-41 pp.7-12 |
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| ICD, IPSJ-ARC | 2006-06-09 10:30 |
Kanagawa | A Reconfigurable Functional Unit for Adaptable Custom Instructions Hamid Noori (Kyushu Univ.), Farhad Mehdipour (Amirkabir Univ. of Tech.), Kazuaki Murakami, Koji Inoue (Kyushu Univ.), Morteza Saheb Zamani (Amirkabir Univ. of Tech.) |
[more] | ICD2006-52 pp.69-74 |
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