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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD | 2016-04-14 10:35 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Lecture]
A 7T-SRAM with Data-Write Technique by Capacitive Coupling Daisaburo Takashima, Masato Endo (Toshiba), Kazuhiro Shimazaki, Manabu Sai (Toshiba Microelectronics), Masaaki Tanino (Toshia Information Systems)  ICD2016-2 |
A 7T-SRAM, in which cell data is written by capacitive coupling, is proposed. The elimination of current-drive in read/w... [more] | ICD2016-2 pp.7-12 |
| ICD | 2014-04-18 10:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
A 7ns-Access-Time 25μW/MHz 128kb SRAM for Low-Power Fast Wake-Up MCU in 65nm CMOS with 27fA/b Retention Current Toshikazu Fukuda, Koji Kohara, Toshiaki Dozaka, Yasuhisa Takeyama, Tsuyoshi Midorikawa (Toshiba), Kenji Hashimoto, Ichiro Wakiyama (TOSMEC), Shinji Miyano, Takehiko Hojo (Toshiba) ICD2014-12 |
Low leakage 128kb SRAM with 65 nm technology that consumes only 3.5nA (27fA/b) in the retention mode is fabricated. Oper... [more] | ICD2014-12 pp.59-64 |
| VLD | 2014-03-04 13:20 |
Okinawa | Okinawa Seinen Kaikan | [Invited Talk]
Advanced Model-Based Hotspot Fix Flow for Layout Optimization with Genetic Algorithm Shuhei Sota (Toshiba Microelectronics), Taiga Uno, Masanari Kajiwara, Chikaaki Kodama (Toshiba), Hirotaka Ichikawa (Toshiba Microelectronics), Ryota Aburada, Toshiya Kotani (Toshiba), Kei Nakagawa, Tamaki Saito (Toshiba Microelectronics) VLD2013-148 |
Under the low-k1 lithography process, many hotspots are generated and their reduction is an urgent issue for mass produc... [more] | VLD2013-148 p.85 |
| VLD | 2014-03-04 14:40 |
Okinawa | Okinawa Seinen Kaikan | Self-Aligned Double and Quadruple Patterning-Aware Grid Routing Chikaaki Kodama (Toshiba), Hirotaka Ichikawa (Toshiba Microelectronics), Fumiharu Nakajima, Koichi Nakayama, Shigeki Nojima, Toshiya Kotani (Toshiba) VLD2013-151 |
Self-Aligned Double and Quadruple Patterning (SADP, SAQP) are leading candidates for sub-$20~nm$ and sub-$14~nm$ node an... [more] | VLD2013-151 pp.99-104 |
| SDM, ICD | 2013-08-02 11:15 |
Ishikawa | Kanazawa University | [Invited Talk]
An LDPC Decoder with Time Domain Analog and Digital Mixed Signal Processing Daisuke Miyashita, Ryo Yamaki (Toshiba), Kazunori Hashiyoshi (Toshiba Microelectronics), Hiroyuki Kobayashi, Shouhei Kousai, Yukihito Oowaki, Yasuo Unekawa (Toshiba) SDM2013-79 ICD2013-61 |
Analog computation is potentially more efficient in certain arithmetic operations since a single wire can represent mult... [more] | SDM2013-79 ICD2013-61 pp.71-76 |
| ICD | 2008-04-17 09:25 |
Tokyo | [Invited Talk]
A Single-Power-Supply 0.7V 1GHz 45nm SRAM with an Asymmetrical Unit β-ratio Memory Cell Takahiko Sasaki, Atsushi Kawasumi, Tomoaki Yabe, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida (Toshiba Corp.), Akihito Tohata (Toshiba Microelectronics Corp.), Akira Katayama, Gou Fukano, Yuki Fujimura, Nobuaki Otsuka (Toshiba Corp.) ICD2008-1 |
A single-power supply $64kB$ SRAM is fabricated in a $45nm$ bulk CMOS technology. The SRAM operates at $1GHz$ with a $0.... [more] | ICD2008-1 pp.1-6 |
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| ICD | 2008-04-17 11:15 |
Tokyo | [Invited Talk]
An 833MHz Pseudo Two-Port Embedded DRAM for Graphics Applications Mariko Kaku, Hitoshi Iwai, Takeshi Nagai, Masaharu Wada, Atsushi Suzuki, Tomohisa Takai, Naoko Itoga, Takayuki Miyazaki, Takayuki Iwai (Toshiba), Hiroyuki Takenaka (Toshiba Microelectronics), Takehiko Hojo, Shinji Miyano, Nobuaki Otsuka (Toshiba) ICD2008-3 |
This paper describes a pseudo two-port embedded DRAM macro developed for graphics applications. It introduces read/write... [more] | ICD2008-3 pp.13-18 |
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| ICD | 2007-04-13 09:10 |
Oita | Floating Body RAM Technology and its Scalability to 32nm Node Hiroomi Nakajima, Naoki Kusunoki, Tomoaki Shino (Toshiba), Tomoki Higashi (TOSMEC), Takashi Ohsawa, Katsuyuki Fujita, Nobuyuki Ikumi, Fumiyoshi Matsuoka, Ryo Fukuda, Yohji Watanabe, Yoshihiro Minami (Toshiba), Atsushi Sakamoto (TJ), Jun Nishimura, Takeshi Hamamoto, Akihiro Nitayama (Toshiba) ICD2007-10 |
Technologies and improved performance of the Floating Body RAM are demonstrated. Reducing SOI thickness to 43nm, a 16Mb ... [more] | ICD2007-10 pp.53-58 |
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| SDM | 2007-03-15 15:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Key Process Technology of Reliable Sub Micron Capacitor for High Density Chain-FeRAM Koji Yamakawa, Tohru Ozaki, Hiroyuki Kanaya, Iwao Kunishima, Yoshinori Kumura, Yoshiro Shimojo, Susumu Shuto, Osamu Hidaka, Yuki Yamada, Soi chi Yamazaki, Takeshi Hamamoto, Shinichiro Shiratake, Daisaburo Takashima, Tadashi Miyakawa, Sumito Ohtsuki (Toshiba) |
[more] | SDM2006-259 pp.27-32 |
| ICD | 2006-04-13 09:45 |
Oita | Oita University | A 65nm Low-Power Embedded DRAM with Extended Data-Retention Sleep Mode Tomohisa Takai, Takeshi Nagai, Masaharu Wada, Hitoshi Iwai, Mariko Kaku, Atsushi Suzuki, Naoko Itoga, Takayuki Miyazaki (Toshiba), Hiroyuki Takenaka (Toshiba Microelectronics), Takehiko Hojo, Shinji Miyano (Toshiba) |
An Extended Data Retention (EDR) sleep mode with on-chip ECC and the MT-CMOS technique is proposed for the embedded DRAM... [more] | ICD2006-2 pp.7-12 |
| ICD | 2006-04-13 11:35 |
Oita | Oita University | Technology development of 128Mb-FBC(Floating Body Cell) Memory by 90nm node CMOS process Hiroomi Nakajima, Yoshihiro Minami, Tomoaki Shino (SoC Center, Toshiba), Atsushi Sakamoto (TJ), Tomoki Higashi (TOSMEC), Naoki Kusunoki, Katsuyuki Fujita, Kosuke Hatsuda, Takashi Ohsawa, Nobutoshi Aoki, Hiroyoshi Tanimoto, Mutsuo Morikado, Kazumi Inoh, Takeshi Hamamoto, Akihiro Nitayama (SoC Center, Toshiba) |
A 128Mb SOI DRAM with FBC (Floating Body Cell) has been successfully developed for the first time. In order to realize f... [more] | ICD2006-5 pp.25-30 |
| ICD | 2005-04-14 11:40 |
Fukuoka | A 128Mb DRAM Using a 1T Gain Cell(FBC) on SOI Takashi Ohsawa, Katsuyuki Fujita, Kosuke Hatsuda (Toshiba), Tomoki Higashi (Toshiba Microelectronics), Mutsuo Morikado, Yoshihiro Minami, Tomoaki Shino, Hiroomi Nakajima, Kazumi Inoh, Takeshi Hamamoto, Shigeyoshi Watanabe (Toshiba) |
We report on a 128Mbit DRAM design using the capacitor-less DRAM cell or the floating body cell(FBC) on SOI. The cell of... [more] | ICD2005-5 pp.23-28 |
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| IE, SIP, ICD, IPSJ-SLDM | 2004-10-22 10:50 |
Yamagata | A DSP Engine for an Extensible Media Embedded Processor Toshiyuki Furusawa (Toshiba Microelectronics), Satoshi Inoue, Isao Katayama, Yoshihisa Arai, Masataka Matsui, Meisei Nishikawa, Takeshi Yoshimoto (Toshiba) |
An extension interface for a configurable processor enabling implementation of an application specific programmable DSP ... [more] | SIP2004-92 ICD2004-124 IE2004-68 pp.19-24 |
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