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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD, SDM | 2009-07-16 15:25 |
Tokyo | Tokyo Institute of Technology | Comprehensive Design Methodology of Dopant Profile to Suppress Gate-LER-induced Threshold Voltage Variability in sub-30 nm NMOSFETs Hidenobu Fukutome (Fujitsu Microelectronics Limited), Yoko Hori (Fujitsu Quality Lab. Limited), Kimihiko Hosaka, Yoichi Momiyama, Shigeo Satoh, Toshihiro Sugii (Fujitsu Microelectronics Limited)  SDM2009-106 ICD2009-22 |
We have demonstrated for the first time that parallel extension implantation tilted along the gate width direction enabl... [more] | SDM2009-106 ICD2009-22 pp.49-52 |
| ED | 2009-06-11 13:00 |
Tokyo | Removal of high dose Ion-Implanted photoresists with SPMless cleaning Toshiya Sato, Tamotsu Suzuki, Akihiko Tsukahara (FML Ltd), Kyota Morihira (Aqua Science Corp) |
[more] | ||
| ICD | 2009-04-13 15:40 |
Miyagi | Daikanso (Matsushima, Miyagi) | [Panel Discussion]
Which memory technology win win the low-VDD race in SoC? Hideto Hidaka (Renesas Tech.), Masanao Yamaoka (Hitachi, Ltd.), Shinji Miyano (Toshiba Corp.), Satoru Akiyama (Hitachi, Ltd.), Tadahiko Sugibayashi (NEC), Syoichiro Kawashima (Fujitsu Limited), Masataka Osaka (Panasonic) ICD2009-4 |
A panel discussion session will high-light low-voltage memory trends, limitations, and future prospects by discussing on... [more] | ICD2009-4 p.19 |
| CAS, CS, SIP | 2009-03-03 13:10 |
Gifu | Nagaragawa Convention Center | [Poster Presentation]
Routing and IPsec Accelerator for a Broadband Router Kazuya Asano, Tomokazu Aoki, Teruhiko Nagatomo, Taku Sugawara, Junichi Hashida, Norio Abe, Satoru Okamoto, Yuya Ueno, Masatoshi Tanabata (FLSFujitsu LSI Solution Limited), Yoshiyuki Okubo (Fujitsu Limited) CAS2008-126 SIP2008-189 CS2008-100 |
We have reported an architecture of a 1Gbps IPsec accelerator previously. In this report, we show that the same LSI can ... [more] | CAS2008-126 SIP2008-189 CS2008-100 pp.145-146 |
| DC | 2009-02-16 10:25 |
Tokyo | A test pattern generation method to reduce the number of detected untestable faults on scan testing Masayoshi Yoshimura (Kyusyu Univ.), Hiroshi Ogawa (Nihon Univ.), Yusyo Omori (Fujitsu Microelectronics), Toshinori Hosokawa (Nihon Univ.), Koji Yamazaki (Meizi Univ.) DC2008-69 |
Scan testing is one of the most popular test method fo VLSIs. In this test, only information of the circuit structure is... [more] | DC2008-69 pp.7-12 |
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| ICD, SDM | 2008-07-18 15:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | High Performance Sub-35 nm Bulk CMOS with Hybrid Gate Structures of NMOS; Dopant Confinement Layer (DCL) / PMOS; Ni-FUSI by Using Flash Lamp Anneal (FLA) in Ni-Silicidation
-- Hybrid Gate Structures -- Hiroyuki Ohta (Fujitsu Lab.), Kazuo Kawamura (FML), Hidenobu Fukutome (Fujitsu Lab.), Mitsugu Tajima, Ken-ichi Okabe (FML), Keiji Ikeda, Kimihiko Hosaka, Yoichi Momiyama, Shigeo Satoh, Toshihiro Sugii (Fujitsu Lab.) SDM2008-148 ICD2008-58 |
We applied Flash Lamp Annealing (FLA) in Ni-silicidation to our developed Dopant Confinement Layer (DCL) structure for t... [more] | SDM2008-148 ICD2008-58 pp.115-120 |
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