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| Chair |
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Moritoshi Yasunaga (Univ. of Tsukuba) |
| Vice Chair |
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Shorin Kyo (Renesas), Minoru Watanabe (Shizuoka Univ.) |
| Secretary |
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Nobuya Watanabe (Okayama Univ.), Yutaka Yamada (Toshiba) |
| Assistant |
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Yoshiki Yamaguchi (Univ. of Tsukuba) |
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| Conference Date |
Tue, Sep 18, 2012 09:30 - 17:20
Wed, Sep 19, 2012 09:00 - 15:30 |
| Topics |
Reconfigurable Systems, etc. |
| Conference Place |
Epock Ritsumei 21, Ritsumeikan Univ. |
| Address |
1-1-1 Noji-higashi, Kusatsu Shiga 525-8577 JAPAN |
| Transportation Guide |
http://www.ritsumei.ac.jp/eng/ |
Contact
Person |
Prof. Tomonori IZUMI |
Tue, Sep 18 AM
09:30 - 10:45 |
| (1) |
09:30-09:55 |
FPGA-based video stabilisation |
Toru Yabuki, Yoshiki Yamaguchi, Yuetsu Kodama (Univ. of Tsukuba) |
| (2) |
09:55-10:20 |
A development of trafic-sign recognition system by using vector processor Venice |
Yoshiya Sugita, Tomoki Tomisawa, Masahiro Fukui (Ritsumeikan Univ.) |
| (3) |
10:20-10:45 |
JPEG encoder design improvement and its evaluation for Dynamic Reconfigurable Circuit |
Hajime Sawano, Nobuyuki Araki, Takashi Kambe (Kinki Univ.) |
| |
10:45-11:10 |
Break ( 25 min. ) |
Tue, Sep 18 AM
11:10 - 12:00 |
| (4) |
11:10-11:35 |
An approach for generating new timbres by the use of an FPGA |
Suguru Ochiai, Yoshiki Yamaguchi, Yuetsu Kodama (Univ. of Tsukuba) |
| (5) |
11:35-12:00 |
An Implementation and Evaluation of SOC Estimation System for Lithium-ion Battery by PSoC |
Masashi Fujimoto, Tatsuya Inoue, Lei Lin, Masahiro Fukui (Ritsumeikan Univ.) |
| |
12:00-13:20 |
Break ( 80 min. ) |
Tue, Sep 18 PM
13:20 - 14:10 |
| (6) |
13:20-14:10 |
[Invited Talk]
The LSI Design Methodology of Tamper Resistant Cryptographic Circuit |
Takeshi Fujino, Mitsuru Shiozaki, Takaya Kubota (Ritsumeikan Univ.), Masaya Yoshikawa (Meijyo Uiv.) |
| |
14:10-14:25 |
Break ( 15 min. ) |
Tue, Sep 18 PM
14:25 - 15:40 |
| (7) |
14:25-14:50 |
Area-Efficeint Design of Asynchronous Circuits Based on Balsa Framework for Synchronous FPGAs |
Masanori Hariyama, Yoshiya Komatsu, Michitaka Kameyama (Tohoku Univ.) |
| (8) |
14:50-15:15 |
Architecture of an Asynchronous FPGA for Handshake-Component-Based Design |
Masanori Hariyama, Yoshiya Komatsu, Michitaka Kameyama (Tohoku Univ.) |
| (9) |
15:15-15:40 |
An Area Minimized Logic Cluster using COGRE Logic Cell |
Toshiya Takahashi, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) |
| |
15:40-16:05 |
Break ( 25 min. ) |
Tue, Sep 18 PM
16:05 - 17:20 |
| (10) |
16:05-16:30 |
Castle of Chips: A reconfigurable technique for multiple chips implementation |
Hideharu Amano (Keio Univ.) |
| (11) |
16:30-16:55 |
Study of "fine-grain dynamic partial reconfiguration mechanism" on FPGA |
Kunihiro Ueda, Naoki Kawamoto, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) |
| (12) |
16:55-17:20 |
Superimposing configuration acceleration method of an optically reconfigurable gate array including a speed adjustment bit |
Takashi yoza, Minoru Watanabe (Shizuoka Univ.) |
Wed, Sep 19 AM
09:00 - 10:15 |
| (13) |
09:00-09:25 |
Effects of Power Saving by Dynamic Partial Reconfiguration in Video Shape Detection Processing |
Naoki Kawamoto, Kunihiro Ueda, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) |
| (14) |
09:25-09:50 |
Fast Flaw Detection of Liquid Crystal Glass with a FPGA Board |
Keisuke Matsuyama, Lin Meng, Yasuo Tenjo, Katsuhiro Yamazaki (Ritsumeikan Univ.) |
| (15) |
09:50-10:15 |
Gray-level image detection of a dynamically reconfigurable vision-chip architecture |
Yuki Kamikubo, Minoru Watanabe, Shoji Kawahito (Shizuoka Univ.) |
| |
10:15-10:40 |
Break ( 25 min. ) |
Wed, Sep 19 AM
10:40 - 11:55 |
| (16) |
10:40-11:05 |
Low-Power Heterogeneous Platform for High Performance Computing and Its Application to 2-D FDTD Computation |
Masanori Hariyama, Waidyasooriya Hasitha Muthumala, Yasuhiro Takei, Michitaka Kameyama (Tohoku Univ.) |
| (17) |
11:05-11:30 |
Prototyping Tightly-Coupled FPGA Cluster for Lattice Boltzmann Computation |
Kentaro Sano, Yoshiaki Kono, Hayato Suzuki, Ryotarro Chiba, Satoru Yamamoto (Tohoku Univ.) |
| (18) |
11:30-11:55 |
OS for Multiple FPGA Clusters which have Different Communication Interfaces |
Akira Kojima, Tetsuo Hironaka (Hiroshima City Univ.) |
| |
11:55-13:15 |
Break ( 80 min. ) |
Wed, Sep 19 PM
13:15 - 14:05 |
| (19) |
13:15-13:40 |
A Design Framework for Reconfigurable IPs with VLSI CADs |
Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) |
| (20) |
13:40-14:05 |
A Circuit Synthesis Algorithm and Evaluation for Coarse Grained Dynamic Reconfigurable Circuits |
Nobuyuki Araki, Takashi Kambe (Kinki Univ.) |
| |
14:05-14:30 |
Break ( 25 min. ) |
Wed, Sep 19 PM
14:15 - 15:30 |
| (21) |
14:15-14:40 |
An implementation and evaluation of variable speed charger for lithium-ion battery by PSoC |
Satoshi Aoki, Hirata Takahito, Masahiro Fukui (Ritsumeikan Univ.) |
| (22) |
14:40-15:05 |
A Virus Scanning Engine Using an MPU and an IGU Based on ROW Shift Decomposition |
Hiroki Nakahara (Kaoghima Univ.), Tsutomu Sasao, Munehiro Matsuura (KIT) |
| (23) |
15:05-15:30 |
Speedup of soft error tolerance evaluation with bootstrap method for FPGA systems |
Kohei Takano, Yoshihiro Ichinomiya, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) |
| Announcement for Speakers |
| General Talk | Each speech will have 20 minutes for presentation and 5 minutes for discussion. |
| Contact Address and Latest Schedule Information |
| RECONF |
Technical Committee on Reconfigurable Systems (RECONF) [Latest Schedule]
|
| Contact Address |
Minoru Watanabe (Shizuoka Univ.)
E- : tmwatan [atmark] ipc.shizuoka.ac.jp
TEL: +81-53-478-1096
FAX: +81-53-478-1096 |
Last modified: 2012-09-08 14:49:22
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