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Technical Committee on VLSI Design Technologies (VLD) (Searched in: 2011)
Search Results: Keywords 'from:2012-03-06 to:2012-03-06'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD | 2012-03-06 10:10 |
Oita | B-con Plaza | Global Process Parameter Estimation Using IDDQ Current Signature Michihiro Shintani, Takashi Sato (Kyoto Univ.)  VLD2011-120 |
[more] | VLD2011-120 pp.1-6 |
| VLD | 2012-03-06 10:35 |
Oita | B-con Plaza | Performance evaluation and Improvement of Via Programmable Logic VPEX Taku Otani, Ryohei Hori, Tatsuya Kitamori, Taisuke Ueoka (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.), Takeshi Fujino (Ritsumeikan Univ.) VLD2011-121 |
We have been studying via programmable structured ASIC architecture “VPEX” which can realize arbitrary logic by customiz... [more] | VLD2011-121 pp.7-12 |
| VLD | 2012-03-06 11:00 |
Oita | B-con Plaza | LSI Implementation of Heterogeneous Multi-Chip Processor for energy-saving Embedded Systems : COOL Chip Hiroyuki Uchida, Michiya Hagimoto, Tomoyuki Morimoto, Nobuyuki Hikichi, Yukoh Matsumoto (TOPS Systems), Fumito Imura, Naoya Watanabe, Katsuya Kikuchi, Motohiro Suzuki, Hiroshi Nakagawa, Masahiro Aoyagi (AIST) VLD2011-122 |
The authors have suggested the low-power embedded heterogeneous multi-chip processor system: COOL Chip. We designed two ... [more] | VLD2011-122 pp.13-17 |
| VLD | 2012-03-06 11:25 |
Oita | B-con Plaza | An Evaluation of the Speedup Method for Power Grid Circuit Simulation by GPGPU Hayato Shiono, Lei Lin, Makoto Yokota, Masahiro Fukui (Ritsumeikan Univ.) VLD2011-123 |
This paper presents an evaluation of the speed-up technique of power grid circuit simulation on GPU. To realize high-pre... [more] | VLD2011-123 pp.19-24 |
| VLD | 2012-03-06 13:10 |
Oita | B-con Plaza | 10G/1G dual-rate EPON OLT LSI with dual encryption modes selected using DBA-information-based algorithm control Sadayuki Yasuda, Takahiro Hatano, Hiroki Suto, Masami Urano, Mamoru Nakanishi, Tsugumichi Shibata (NTT) VLD2011-124 |
For next-generation optical access systems, we developed a 10G/1G dual-rate EPON OLT LSI that fully conforms to the IEEE... [more] | VLD2011-124 pp.25-30 |
| VLD | 2012-03-06 13:35 |
Oita | B-con Plaza | Implementation of Tamper-Resistant Cryptographic DES Circuit using Dual-Rail RSL Memory Megumi Shibatani, Katsuhiko Iwai, Mitsuru Shiozaki, Shunsuke Asagawa, Takeshi Fujino (Ritsumeikan Univ.) VLD2011-125 |
[more] | VLD2011-125 pp.31-36 |
| VLD | 2012-03-06 14:00 |
Oita | B-con Plaza | A loop pipeling method for irregular nested loops Takashi Takenaka, Kazutoshi Wakabayashi (NEC), Yuka Nakagoshi (NIS) VLD2011-126 |
This paper presents a behavioral synthesis method for pipelining irregular nested loops. An irregular nested loop is ... [more] |
VLD2011-126 pp.37-42 |
| VLD | 2012-03-06 14:25 |
Oita | B-con Plaza | Resource Binding for Datapaths with Improved Post-Silicon Skew Tunability Yosuke Haruta, Mineo Kaneko (JAIST) VLD2011-127 |
With the progress of fabrication-process technology, the variation of signal transmission delay due to variations in pro... [more] | VLD2011-127 pp.43-48 |
| VLD | 2012-03-06 15:05 |
Oita | B-con Plaza | High-Level Synthesis for Mixed Behavioral-Level/RTL Design Descriptions Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo) VLD2011-128 |
It is widely known that high-level synthesis technology can improve the design productivity dramatically by raising the ... [more] | VLD2011-128 pp.49-54 |
| VLD | 2012-03-06 15:30 |
Oita | B-con Plaza | CDFG Transformation Based on Speculation Exploiting Implicit Parallelism in Behavioral Synthesis Shinji Ohno (Nagoya Univ.), Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ.) VLD2011-129 |
In recent years, circuit design in languages with higher abstraction level has been widely noticed to address the proble... [more] | VLD2011-129 pp.55-60 |
| VLD | 2012-03-06 15:55 |
Oita | B-con Plaza | Utilization of Register Transfer Level False Paths for Logic Optimization with Logic Synthesis Tools Takehiro Mikami, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2011-130 |
A circuit has many false paths on which signal transitions never affect its circuit behavior.This report proposes a logi... [more] | VLD2011-130 pp.61-66 |
| VLD | 2012-03-06 16:20 |
Oita | B-con Plaza | A Length Matching Routing Algorithm on Single Layer Using Longer Path Algorithm for Single Net Syouhei Furuyama, Yukihide Kohira (UoA) VLD2011-131 |
Due to the increase of operation frequency in recent LSI systems, signal propagation delays are required to achieve spec... [more] | VLD2011-131 pp.67-72 |
| VLD | 2012-03-07 09:15 |
Oita | B-con Plaza | A Power Grid Optimization Algorithm Considering by NBTI Yoriaki Nagata, Masahiro Fukui (Ritsumeikan Univ.), Shuji Tsukiyama (Chuo Univ.) VLD2011-132 |
With the advent of super deep submicron age and high integration, the circuit was concerned about the impact of timing ... [more] | VLD2011-132 pp.73-78 |
| VLD | 2012-03-07 09:40 |
Oita | B-con Plaza | Design automation of highly reliable VLSI by redundancy FF replacement method Ken Yano, Takahito Yoshiki, Takanori Hayashida, Toshinori Sato (Fukuokadai) VLD2011-133 |
Design automation of highly reliable VLSI using canary FF is proposed. Canary FF is used to detect timing error caused f... [more] | VLD2011-133 pp.79-84 |
| VLD | 2012-03-07 10:05 |
Oita | B-con Plaza | An Efficient Method to Analyze Logic Masking Effects of Soft Errors in Sequential Circuits Taiga Takata, Yusuke Matsunaga (Kyushu Univ.) VLD2011-134 |
[more] | VLD2011-134 pp.85-90 |
| VLD | 2012-03-07 10:45 |
Oita | B-con Plaza | Equivalence Checking Method of Timed Logic Formulae for Design Verification of Single-Flux Quantum Circuits Takahiro Kawaguchi (Nagoya Univ.), Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ.) VLD2011-135 |
This paper proposes an equivalence checking method of timed logic formulae for reducing number of states in verificatio... [more] |
VLD2011-135 pp.91-96 |
| VLD | 2012-03-07 11:10 |
Oita | B-con Plaza | Implmentation of Look-ahead Assertion for Pattern-independent Regular Expression Matching Engine Yoichi Wakaba, Shinobu Nagayama, Masato Inagi, Shin'ichi Wakabayashi (Hiroshima City Univ.) VLD2011-136 |
In this paper, we propose a look-ahead assertion matching method for regular expression matching hardware engine. In net... [more] | VLD2011-136 pp.97-102 |
| VLD | 2012-03-07 11:35 |
Oita | B-con Plaza | An Implementation of Real-time Image Recognition Hardware for Many Cameras Eiichi Hosoya, Takashi Aoki, Takuya Otsuka, Yusuke Sekihara, Akira Onozawa (NTT) VLD2011-137 |
Real-time object recognition for many cameras is becoming important in many surveillance applications. Image recognition... [more] | VLD2011-137 pp.103-108 |
| VLD | 2012-03-07 13:20 |
Oita | B-con Plaza | Power reduction of memory circuit and DVFS technique in Dynamic Reconfigurable Processor Yuki Hayakawa, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2011-138 |
This paper describes a DVFS technique to reduce energy dissipation of Dynamically Reconfigurable Processors(DRP). DRP’s ... [more] | VLD2011-138 pp.109-114 |
| VLD | 2012-03-07 13:45 |
Oita | B-con Plaza | A GPGPU Implementation of Approximate Regular Expression Matching Algorithm and Comparison with an FPGA Implementation Yuichiro Utan, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi (Hiroshima City Univ.) VLD2011-139 |
Recently, to conduct more advanced approximate string matching, a systolic hardware algorithm for approximate string mat... [more] | VLD2011-139 pp.115-120 |
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