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Technical Committee on VLSI Design Technologies (VLD)  (2018 - )

Chair: Noriyuki Minegishi (Mitsubishi Electric) Vice Chair: Nozomu Togawa (Waseda Univ.)
Secretary: Koyo Nitta (NTT), Yukihide Kohira (Univ. of Aizu)

[Go to Official VLD Homepage (Japanese)] 
 Schedule  (Sort by: Date Ascending)
 Results 1 - 4 of 4  /   
Date Place Topics Joint Deadline Select Menu
Wed, Dec 5, 2018
- Fri, Dec 7
Satellite Campus Hiroshima Design Gaia 2018 -New Field of VLSI Design- VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
[Mon, Oct 8]
  • Detailed Info.
       (Japanese)
  • Regist. Closed
  • Adv. Program
  • Registration Fee 
  • Wed, Jan 30, 2019
    - Thu, Jan 31
    Raiosha, Hiyoshi Campus, Keio University FPGA Applications, etc. IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] [Sun, Nov 25]
  • Detailed Info.
  • Regist. Closed
  • Adv. Program
  • Registration Fee 
  • Wed, Feb 27, 2019
    - Sat, Mar 2
    Okinawa Ken Seinen Kaikan Design Technology for System-on-Silicon, Hardware Security, etc. HWS [Tue, Dec 18]
  • Regist. Closed
  • Adv. Program
  • Registration Fee 
  • Wed, May 15, 2019
    Ookayama Campus, Tokyo Institute of Technology System Design, etc. IPSJ-SLDM [Mon, Mar 11]
  • Detailed Info.
       (Japanese)
  • Registration
       for presentation
  • Registration Fee 
  •  Results 1 - 4 of 4  /   


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