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Technical Committee on VLSI Design Technologies (VLD)  (2017 - )

Chair: Hiroyuki Ochi (Ritsumeikan Univ.) Vice Chair: Noriyuki Minegishi (Mitsubishi Electric)
Secretary: Shinobu Nagayama (Hiroshima City Univ.), Koyo Nitta (NTT)

[Go to Official VLD Homepage (Japanese)] 
 Schedule  (Sort by: Date Ascending)
 Results 1 - 3 of 3  /   
Date Place Topics Joint Deadline Select Menu
Mon, Nov 6, 2017
- Wed, Nov 8
Kumamoto-Kenminkouryukan Parea Design Gaia 2017 -New Field of VLSI Design- VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
[Mon, Sep 11]
  • Detailed Info.
       (Japanese)
  • Regist. Closed
  • Adv. Program 
  • Thu, Jan 18, 2018
    - Fri, Jan 19 (tentative)
    Raiosha, Hiyoshi Campus, Keio University FPGA Applications, etc IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] [Mon, Nov 20]
  • Detailed Info.
  • Regist. Closed
  • Adv. Program
  • Participation Fee 
  • Wed, Feb 28, 2018
    - Fri, Mar 2
    Okinawa Seinen Kaikan     [Mon, Jan 15]
  • Detailed Info.
       (Japanese)
  • Registration
       for presentation
     
  •  Results 1 - 3 of 3  /   


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