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Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Kimiyoshi Usami (Shibaura Inst. of Tech.)
Vice Chair Akihisa Yamada (Sharp)
Secretary Kazutoshi Kobayashi (Kyoto Inst. of Tech.), Takashi Takenaka (NEC)

Conference Date Tue, Mar 6, 2012 10:10 - 16:45
Wed, Mar 7, 2012 09:15 - 16:30
Topics Design Methodologies for System-on-a-chip 
Conference Place B-con Plaza 
Address 12-1, Yamanote-cho, Beppu-Shi, Oita, 874-0828, Japan
Transportation Guide 15 minutes walk from Beppu (Oita) Station or 5 minutes by bus
http://www.b-conplaza.jp/english/index.htm
Contact
Person
Prof. Yasuhiro Takashima
+81-977-26-7111 (Conference Venue)
Announcement International Conference SASIMI( http://www.sasimi.jp/ ) will be held at B-con Plaza from Mar. 8th to 9th just after our technical meeting.
We will have a party on Jan. 25th. Fee is 4,000Yen for non-students, and 3,000Yen for Student. Details are http://www.ieice.org/~vld/

Tue, Mar 6 AM  Power Grid Analysis
Chair: Nozomu Togawa (Waseda Univ.)
10:10 - 11:50
(1) 10:10-10:35 Global Process Parameter Estimation Using IDDQ Current Signature Michihiro Shintani, Takashi Sato (Kyoto Univ.)
(2) 10:35-11:00 Performance evaluation and Improvement of Via Programmable Logic VPEX Taku Otani, Ryohei Hori, Tatsuya Kitamori, Taisuke Ueoka (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.), Takeshi Fujino (Ritsumeikan Univ.)
(3) 11:00-11:25 LSI Implementation of Heterogeneous Multi-Chip Processor for energy-saving Embedded Systems : COOL Chip Hiroyuki Uchida, Michiya Hagimoto, Tomoyuki Morimoto, Nobuyuki Hikichi, Yukoh Matsumoto (TOPS Systems), Fumito Imura, Naoya Watanabe, Katsuya Kikuchi, Motohiro Suzuki, Hiroshi Nakagawa, Masahiro Aoyagi (AIST)
(4) 11:25-11:50 An Evaluation of the Speedup Method for Power Grid Circuit Simulation by GPGPU Hayato Shiono, Lei Lin, Makoto Yokota, Masahiro Fukui (Ritsumeikan Univ.)
Tue, Mar 6 PM  Cipher and High-level Synthesis
Chair: Hiroaki Yoshida (Univ. of Tokyo)
13:10 - 14:50
(5) 13:10-13:35 10G/1G dual-rate EPON OLT LSI with dual encryption modes selected using DBA-information-based algorithm control Sadayuki Yasuda, Takahiro Hatano, Hiroki Suto, Masami Urano, Mamoru Nakanishi, Tsugumichi Shibata (NTT)
(6) 13:35-14:00 Implementation of Tamper-Resistant Cryptographic DES Circuit using Dual-Rail RSL Memory Megumi Shibatani, Katsuhiko Iwai, Mitsuru Shiozaki, Shunsuke Asagawa, Takeshi Fujino (Ritsumeikan Univ.)
(7) 14:00-14:25 A loop pipeling method for irregular nested loops Takashi Takenaka, Kazutoshi Wakabayashi (NEC), Yuka Nakagoshi (NIS)
(8) 14:25-14:50 Resource Binding for Datapaths with Improved Post-Silicon Skew Tunability Yosuke Haruta, Mineo Kaneko (JAIST)
Tue, Mar 6 PM  Behavioral Synthesis and Place/Route
Chair: Atsushi Takahashi (Osaka Univ.)
15:05 - 16:45
(9) 15:05-15:30 High-Level Synthesis for Mixed Behavioral-Level/RTL Design Descriptions Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo)
(10) 15:30-15:55 CDFG Transformation Based on Speculation Exploiting Implicit Parallelism in Behavioral Synthesis Shinji Ohno (Nagoya Univ.), Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ.)
(11) 15:55-16:20 Utilization of Register Transfer Level False Paths for Logic Optimization with Logic Synthesis Tools Takehiro Mikami, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)
(12) 16:20-16:45 A Length Matching Routing Algorithm on Single Layer Using Longer Path Algorithm for Single Net Syouhei Furuyama, Yukihide Kohira (UoA)
Wed, Mar 7 AM  Reliability
Chair: Kazutoshi Kobayashi (KIT)
09:15 - 10:30
(13) 09:15-09:40 A Power Grid Optimization Algorithm Considering by NBTI Yoriaki Nagata, Masahiro Fukui (Ritsumeikan Univ.), Shuji Tsukiyama (Chuo Univ.)
(14) 09:40-10:05 Design automation of highly reliable VLSI by redundancy FF replacement method Ken Yano, Takahito Yoshiki, Takanori Hayashida, Toshinori Sato (Fukuokadai)
(15) 10:05-10:30 An Efficient Method to Analyze Logic Masking Effects of Soft Errors in Sequential Circuits Taiga Takata, Yusuke Matsunaga (Kyushu Univ.)
Wed, Mar 7 AM  Circuit and Systems
Chair: Takeshi Takenaka (NEC)
10:45 - 12:00
(16) 10:45-11:10 Equivalence Checking Method of Timed Logic Formulae for Design Verification of Single-Flux Quantum Circuits Takahiro Kawaguchi (Nagoya Univ.), Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ.)
(17) 11:10-11:35 Implmentation of Look-ahead Assertion for Pattern-independent Regular Expression Matching Engine Yoichi Wakaba, Shinobu Nagayama, Masato Inagi, Shin'ichi Wakabayashi (Hiroshima City Univ.)
(18) 11:35-12:00 An Implementation of Real-time Image Recognition Hardware for Many Cameras Eiichi Hosoya, Takashi Aoki, Takuya Otsuka, Yusuke Sekihara, Akira Onozawa (NTT)
Wed, Mar 7 PM  Reconfigurable Systems
Chair: Kazuyoshi Takagi (Kyoto Univ.)
13:20 - 15:00
(19) 13:20-13:45 Power reduction of memory circuit and DVFS technique in Dynamic Reconfigurable Processor Yuki Hayakawa, Kimiyoshi Usami (Shibaura Institute of Tech.)
(20) 13:45-14:10 A GPGPU Implementation of Approximate Regular Expression Matching Algorithm and Comparison with an FPGA Implementation Yuichiro Utan, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi (Hiroshima City Univ.)
(21) 14:10-14:35 Power Efficient Design of Arithmetic Circuits Based on Embedded Memory Blocks in FPGA Xinmu Yu (Waseda Univ.), Kiyoharu Hamaguchi (Osaka Univ.), Shinji Kimura (Waseda Univ.)
(22) 14:35-15:00 Performance of the Evaluation of a Variable-Latency-Circuit on FPGA Yuuta Ukon, Kenta Ando, Atsushi Takahashi (Osaka Univ)
Wed, Mar 7 PM  Low-Power Design
Chair: Shigetoshi Nakatake (Univ. of Kitakyushu)
15:15 - 16:30
(23) 15:15-15:40 Power-Switch Drive-circuit generation for Ground-Bounce reduction using the Genetic-Programming Makoto Miyauchi, Masaru Kudo, Yuya Ohta, Kimiyoshi Usami (Shibaura Institute of Tech.)
(24) 15:40-16:05 A Design of Low-Power Color Interporation Circuits Based on Color Difference Kouta Omobayashi, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)
(25) 16:05-16:30 Leakage Energy Reduction of Sub-Threshold Circuits by Body Bias Control for Power Switch Ryo Mitsuhashi, Masaru Kudo, Yuya Ohta, Kimiyoshi Usami (Shibaura Institute of Tech.)

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address Kazutoshi Kobayashi (Kyoto Institute of Technology)
E-: bat
Tel: +81-75-724-7452 
Announcement See also VLD's homepage:
http://www.ieice.org/~vld/


Last modified: 2012-03-06 15:16:07


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