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Technical Committee on Computer Systems (CPSY) [schedule] [select]
Chair Yasunori Kimura
Vice Chair Nobuki Kajihara, Toshinori Sueyoshi
Secretary Tsutomu Yoshinaga, Hiroko Midorikawa
Assistant Hideki Okawara

Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Michiaki Muraoka
Vice Chair Shinji Kimura
Secretary Ryuichi Yamaguchi, Yusuke Matsunaga

Technical Committee on Reconfigurable Systems (RECONF) [schedule] [select]
Chair Toshinori Sueyoshi
Vice Chair Akira Nagoya, Hideharu Amano
Secretary Tetsuo Hironaka, Morihiro Kuga

Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) [schedule] [select]
Chair Takashi Kambe
Secretary Minoru Inamori, Masato Edahiro, Shinji Kimura

Conference Date Tue, Jan 25, 2005 09:30 - 17:20
Wed, Jan 26, 2005 09:30 - 17:50
Topics FPGA and its Application, etc 
Conference Place  

Tue, Jan 25 AM 
09:30 - 12:00
(1) 09:30-10:00 A Reconfigurable Processor based on ALU array architecture with limitation on the interconnection Makoto Okada, Tatsuo Hiramatsu, Hiroshi Nakajima, Makoto Ozone, Katsunori Hirase (SANYO Electric), Shinji Kimura (Waseda Univ.)
(2) 10:00-10:30 Reconfigurable 1-bit processor array with reduced wiring area Nobuo Nakai, Masaki Nakanishi, Shigeru Yamashita, Katsumasa Watanabe (NAIST)
(3) 10:30-11:00 A variable clock mechanism for Dynamically Reconfigurable Processors Hideharu Amano, Yoshinori Adachi, Satoshi Tsutsumi, Kenichiro Ishikawa (Keio Univ.)
(4) 11:00-11:30 An asynchronous multi-context device with new context switching method Yoshinori Adachi, Satoshi Tsutsumi, Hideharu Amano (Keio Univ.)
(5) 11:30-12:00 A Discussion on Fault Tolerance of Dynamic Reconfigurable Device Naoki Ochi, Kentaro Nakahara, Futoshi Morie, Shin'ichi Kouyama, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura (Kyoto Univ.)
  12:00-13:00 Lunch Break ( 60 min. )
Tue, Jan 25 PM 
13:00 - 14:00
(6) 13:00-13:30 [Invited Talk]
Basics and Goals of Assertion-Based Verification
Kiyoharu Hamaguchi (Osaka Univ.)
(7) 13:30-14:00 [Invited Talk]
*
Masanori Imai (STARC)
  14:00-14:10 Break ( 10 min. )
Tue, Jan 25 PM 
14:10 - 15:10
(8) 14:10-14:40 A dividing technique of assertions for an interface protocol used in a divide and conquer approach of formal verification Hironao Matsushima, Akira Kitajima (OECU)
(9) 14:40-15:10 Crosstalk Driven Placement Procedure Masakazu Ochiai, Masaya Yoshikawa, Takeshi Fujino, Hidekazu Terai (Ritsumeikan University)
  15:10-15:20 Break ( 10 min. )
Tue, Jan 25 PM 
15:20 - 17:20
(10) 15:20-15:50 An Instance-Specific Hardware Algorithm Using FPGAs for the Mimimum Vertex Cover Problem of a Graph Kenji Kikuchi, Shin'ichi Wakabayashi (Hiroshima City Univ.)
(11) 15:50-16:20 Solving SAT problem by PCMGTP on FPGA Shohei Kinoshita, Junichi Matsuda, Hiroshi Fujita, Miyuki Koshimura, Ryuzo Hasegawa (Kyushu Univ)
(12) 16:20-16:50 Design of cellular simulation platform for SBML model Yow Iwaoka, Yasunori Osana, Tomonori Fukushima, Masato Yoshimi (Keio Univ.), Akira Funahashi, Noriko Hiroi (JST), Yuichiro Shibata, Naoki Iwanaga (Nagasaki Univ.), Hiroaki Kitano (JST), Hideharu Amano (Keio Univ.)
(13) 16:50-17:20 Architecture for Crossover based on Sequence Pair Ryousuke Kanemitsu, Akinori Bito, Masaya Yoshikawa, Hidekazu Terai (Ritsumeikan University)
Wed, Jan 26 AM 
09:30 - 12:00
(14) 09:30-10:00 Preliminary Implementation of Volume Rendering Circuit onto an FPGA-based Visualization Accelerator Dai Okamura, Masahiro Goshima, Shin-ichiro Mori, Yasuhiko Nakashima, Shinji Tomita (Kyoto Univ.)
(15) 10:00-10:30 Hardware Realization of Panoramic Image Generation Function Yukinori Nagase, Takao Kawamura, Kazunori Sugahara (Tottori Univ.)
(16) 10:30-11:00 Hardware Realization of Active Contour Model and Its Application for Word Recognition by Lip Reading Yusuke Sasaki, Takao Kawamura, Kazunori Sugahara (Tottori Univ.)
(17) 11:00-11:30 FPGA-based Sound Analysis System for the Marine Organism Yuki Shimizu (Waseda Univ.), Rajendar Bahl (IIT), Masao Sakata, Tamaki Ura (Tokyo Univ.), Masao Yanagisawa (Waseda Univ.)
(18) 11:30-12:00 Detection of the audio watermark on FPGA Kazuhiro Sakakibara, Yasushi Inoguchi (JAIST)
  12:00-13:00 Lunch Break ( 60 min. )
Wed, Jan 26 PM 
13:00 - 13:30
(19) 13:00-13:30 [Invited Talk]
*
Takashi Miyamori (TOSHIBA)
  13:30-13:40 Break ( 10 min. )
Wed, Jan 26 PM 
13:40 - 16:10
(20) 13:40-14:10 Design and Development of Microprocessors on a Hardware/Software Colearning System Koichiro Nakamura, Hoang Anh Tuan, Shigeru Oyanagi, Katsuhiro Yamazaki (Ritsumeikan University)
(21) 14:10-14:40 Performance Evaluation of Speculative Thread Execution in the Single-Chip Multiprocessor SKY Akio Kamimurai, Ryotaro Kobayashi, Hideki Ando, Toshio Shimada (Nagoya Univ.)
(22) 14:40-15:10 ASIP Architecture for Real-Time Graphical Effect Acceleration Tatsuhiro Yoshimura, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.)
(23) 15:10-15:40 Extraction of Instruction Latency from Cycle-True Processor Models Yusuke Hiraoka, Nagisa Ishiura (Kwansei Gakuin Univ.), Masaharu Imai (Osaka Univ)
(24) 15:40-16:10 Instruction Pattern Generation for Retargetable Compiler Atsushi Kishimoto, Nagisa Ishiura, Yuuki Masui (Kwansei Gakuin Univ.), Masaharu Imai (Osaka Univ.)
  16:10-16:20 Break ( 10 min. )
Wed, Jan 26 PM 
16:20 - 17:50
(25) 16:20-16:50 Proposal and Implementation of Framework for Self-reproductive applications on PCA Tomoki Kamiyama, Keigo Kurata, Yousuke Ikehata, Junji Kitamichi, Kenichi Kuroda (Univ.Aizu)
(26) 16:50-17:20 A Design of AES Encryption Circuit with 128-bit keys Using Look-Up Table Ring Hui Qin, Tsutomu Sasao (Kyushu Inst. of Tech.), Yukihiro Iguchi (Meiji Univ.)
(27) 17:20-17:50 Architecture of RNS to Mixed-Radix Number Converter Using Signed-Digit Number Arithmetic Yumi Ogawa, Shuangching Chen, Shugang Wei (Gunma Univ.)

Contact Address and Latest Schedule Information
CPSY Technical Committee on Computer Systems (CPSY)   [Latest Schedule]
Contact Address  
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address  
Announcement You will see the latest information at the below WEB page.
http://www.ieice.org/~vld/index.html
RECONF Technical Committee on Reconfigurable Systems (RECONF)   [Latest Schedule]
Contact Address  
IPSJ-SLDM Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM)   [Latest Schedule]
Contact Address  


Last modified: 2004-12-17 10:01:19


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