|
|
| Chair |
|
Masato Motomura (Hokkaido Univ.) |
| Vice Chair |
|
Yuichiro Shibata (Nagasaki Univ.), Kentaro Sano (Tohoku Univ.) |
| Secretary |
|
Kazuya Tanigawa (Hiroshima City Univ.), Takefumi Miyoshi (e-trees.Japan) |
| Assistant |
|
Yuuki Kobayashi (NEC), Hiroki Nakahara (Tokyo Inst. of Tech.) |
|
| Conference Date |
Mon, Sep 25, 2017 10:30 - 17:30
Tue, Sep 26, 2017 10:00 - 14:45 |
| Topics |
Reconfigurable Systems, etc. |
| Conference Place |
|
| Transportation Guide |
東銀座駅（日比谷線, 浅草線）5番出口より徒歩3分
https://www.doorkeeper.jp/%E4%BC%9A%E5%A0%B4/dwango |
Contact
Person |
Takayoshi Katsumata |
Copyright
and
reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
| Notes on Review |
This article is a technical report without peer review, and its polished version will be published elsewhere. |
Mon, Sep 25 AM
10:30 - 11:20 |
| (1) |
10:30-10:55 |
Pattern-matching-based game strategies and the strategy difference in pattern sizes  RECONF2017-22 |
Masataka Nakano, Yoshiki Yamaguchi (Univ. of Tsukuba) |
| (2) |
10:55-11:20 |
A thorough investigation of FPGA performance for PCIe Gen3 communication RECONF2017-23 |
Hiroki Nakamura, Hirotaka Takayama, Yoshiki Yamaguchi, Taisuke Boku (Univ. of Tsukuba) |
Mon, Sep 25 PM
13:30 - 14:45 |
| (3) |
13:30-13:55 |
RECONF2017-24 |
|
| (4) |
13:55-14:20 |
A Study of Applicability of FPGA Dynamic Partial Reconfiguration Technique on COTS-based Carrier Network Equipment with HW/SW Co-design Scheme RECONF2017-25 |
Toru Homemoto, Hisaharu Ishii, Toshiya Matsuda, Masaru Katayama, Kazuyuki Matsumura (NTT) |
| (5) |
14:20-14:45 |
A Memory Reduction with Neuron Pruning for a Binarized Deep Convolutional Neural Network: Its FPGA Realization RECONF2017-26 |
Tomoya Fujii, Shimpei Sato, Hiroki Nakahara (Tokyo Inst. of Tech.) |
Mon, Sep 25 PM
15:00 - 16:15 |
| (6) |
15:00-15:25 |
Hardware acceleration for holographic memories on optically reconfigurable gate arrays RECONF2017-27 |
Takumi Fujimori, Minoru Watanabe (Shizuoka Univ.) |
| (7) |
15:25-15:50 |
Proplsal of reconfigurable system LSI with BiCS technology
-- Application to combination logic, FF, CMOS circuit and FPGA -- RECONF2017-28 |
Shigeyoshi Watanabe (Shonan Inst. of Tech.), Tomohiro Yokota (DNP Data Techno), Shouto Tamai (Oi Electric), Takumi Sato (Japan Business Systems) |
| (8) |
15:50-16:15 |
Performance analysis of Mono-Instruction Set Computer using VTR RECONF2017-29 |
Hiroki Shinba, Minoru Watanabe (Shizuoka Univ.) |
Mon, Sep 25 PM
16:30 - 17:30 |
| (9) |
16:30-17:30 |
[Invited Talk]
Scalable and convertible FPGA DNN accelerator RECONF2017-30 |
Shinichi Suto, Takato Yamada (LeapMind) |
Tue, Sep 26 AM
10:00 - 10:50 |
| (10) |
10:00-10:25 |
GUINNESS: A GUI based Binarized Deep Neural Network Framework for an FPGA RECONF2017-31 |
Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Masayuki Shimoda, Shimpei Sato (Tokyo Inst. of Tech.) |
| (11) |
10:25-10:50 |
High-speed Calculation of k-means Clustering Using FPGA and its Application to Pick and Place Machine RECONF2017-32 |
Shogo Nakamura, Hiroki Ebara, Kenji Kanazawa (Univ. of Tsukuba), Noriyuki Aibe (Keio Univ.), Moritoshi Yasunaga (Univ. of Tsukuba) |
Tue, Sep 26 AM
11:00 - 12:00 |
| (12) |
11:00-12:00 |
[Invited Talk]
Increasing Productivity Using Xilinx Development Tools RECONF2017-33 |
Louie Valena (Xilinx) |
Tue, Sep 26 PM
13:30 - 14:45 |
| (13) |
13:30-13:55 |
RECONF2017-34 |
|
| (14) |
13:55-14:20 |
A case study of High-level Synthesis Using Higher-order Function on Functional Language RECONF2017-35 |
Takuya Teraoka, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) |
| (15) |
14:20-14:45 |
Implementing RISC-V with a Python-Based High-Level Synthesis Compiler RECONF2017-36 |
Ryouzaburo Suzuki, Hiroaki Kataoka (Sinby) |
| Announcement for Speakers |
| General Talk | Each speech will have 20 minutes for presentation and 5 minutes for discussion. |
| Contact Address and Latest Schedule Information |
| RECONF |
Technical Committee on Reconfigurable Systems (RECONF) [Latest Schedule]
|
| Contact Address |
Inquiries for RECONF
Masato Motomura (Hokkaido Univ.) :      ist    i
Inquiries for the Meeting in Sep. 2017
Takefumi MIYOSHI (e-trees.Japan, Inc.) :     n |
Last modified: 2017-09-15 09:47:45
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