Paper Abstract and Keywords |
Presentation |
2017-12-14 13:20
Seiya Akaki, Hidetsugu Irie, Shuichi Sakai (UT) CAS2017-71 ICD2017-59 CPSY2017-68 Link to ES Tech. Rep. Archives: ICD2017-59 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
The single thread performance of a processor supports the entire system capability by reducing the critical path latency of the program.STRAIGHT has been developed as a processor architecture to improve single thread performance.STRAIGHT has a unique instruction format of specyfying source operands by instruction distance. This removes register renaming and makes it possible to construct an efficient Out-of-Order execution mechanism.This paper proposes the configuration of the scheduling logic using the instruction format of STRAIGHT. The proposed STRAIGHT scheduler simplify its hardware by using the fact that the operand is expressed as instruction distance. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
microarchitecture / CPU / scheduler / hardware / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 117, no. 345, CPSY2017-68, pp. 43-44, Dec. 2017. |
Paper # |
CPSY2017-68 |
Date of Issue |
2017-12-07 (CAS, ICD, CPSY) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
CAS2017-71 ICD2017-59 CPSY2017-68 Link to ES Tech. Rep. Archives: ICD2017-59 |
Conference Information |
Committee |
ICD CPSY CAS |
Conference Date |
2017-12-14 - 2017-12-15 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Art Hotel Ishigakijima |
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Paper Information |
Registration To |
CPSY |
Conference Code |
2017-12-ICD-CPSY-CAS |
Language |
Japanese without English title) |
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(See Japanese page) |
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Keyword(1) |
microarchitecture |
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CPU |
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scheduler |
Keyword(4) |
hardware |
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1st Author's Name |
Seiya Akaki |
1st Author's Affiliation |
The University of Tokyo (UT) |
2nd Author's Name |
Hidetsugu Irie |
2nd Author's Affiliation |
The University of Tokyo (UT) |
3rd Author's Name |
Shuichi Sakai |
3rd Author's Affiliation |
The University of Tokyo (UT) |
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Speaker |
Author-1 |
Date Time |
2017-12-14 13:20:00 |
Presentation Time |
20 minutes |
Registration for |
CPSY |
Paper # |
CAS2017-71, ICD2017-59, CPSY2017-68 |
Volume (vol) |
vol.117 |
Number (no) |
no.343(CAS), no.344(ICD), no.345(CPSY) |
Page |
pp.43-44 |
#Pages |
2 |
Date of Issue |
2017-12-07 (CAS, ICD, CPSY) |
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