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| Presentation | 2017-12-14 10:10 Design of Non-Binary SAR ADC with Noise-Tunable Comparator Takaaki Ito, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada (The Univ. of Tokyo)  CAS2017-65 ICD2017-53 CPSY2017-62 Link to ES Tech. Rep. Archives: ICD2017-53 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | A 16-bit non-binary SAR ADC with a noise-tunable comparator for low power consumption is presented. A non-binary-weighted capacitive DAC with redundancy is used in the ADC to suppress the impact of incomplete settling, capacitor mismatch and kickback from the comparator. A tri-level DAC that reduces switching power improves ADC's power efficiency. A dynamic comparator is designed to implement noise tunability so that the comparator noise level is controlled during conversion depending on the DAC redundancy range to save power consumption. The ADC performance is estimated in simulation with standard CMOS 0.18,$mu$m technology, which shows THD of $-$93.1,dB at Nyquist input while it consumes 32.92,$mu$W that results in 39.0,fJ/conv.-step FoM. 31.9,% power reduction is achieved by the proposed noise-tunable comparator. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | successive approximation register / analog-to-digital converter / regenerative comparator / noise tuning / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 117, no. 344, ICD2017-53, pp. 9-13, Dec. 2017. | |
| Paper # | ICD2017-53 | |
| Date of Issue | 2017-12-07 (CAS, ICD, CPSY) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CAS2017-65 ICD2017-53 CPSY2017-62 Link to ES Tech. Rep. Archives: ICD2017-53 |
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| Conference Information | |
| Committee | ICD CPSY CAS |
| Conference Date | 2017-12-14 - 2017-12-15 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Art Hotel Ishigakijima |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2017-12-ICD-CPSY-CAS |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design of Non-Binary SAR ADC with Noise-Tunable Comparator |
| Sub Title (in English) | |
| Keyword(1) | successive approximation register |
| Keyword(2) | analog-to-digital converter |
| Keyword(3) | regenerative comparator |
| Keyword(4) | noise tuning |
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| 1st Author's Name | Takaaki Ito |
| 1st Author's Affiliation | The University of Tokyo (The Univ. of Tokyo) |
| 2nd Author's Name | Tetsuya Iizuka |
| 2nd Author's Affiliation | The University of Tokyo (The Univ. of Tokyo) |
| 3rd Author's Name | Toru Nakura |
| 3rd Author's Affiliation | The University of Tokyo (The Univ. of Tokyo) |
| 4th Author's Name | Kunihiro Asada |
| 4th Author's Affiliation | The University of Tokyo (The Univ. of Tokyo) |
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| Speaker | Author-1 |
| Date Time | 2017-12-14 10:10:00 |
| Presentation Time | 20 minutes |
| Registration for | ICD |
| Paper # | CAS2017-65, ICD2017-53, CPSY2017-62 |
| Volume (vol) | vol.117 |
| Number (no) | no.343(CAS), no.344(ICD), no.345(CPSY) |
| Page | pp.9-13 |
| #Pages | 5 |
| Date of Issue | 2017-12-07 (CAS, ICD, CPSY) |
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