IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2017-04-21 09:35
[Invited Lecture] Architectures and energy performance of nonvolatile SRAM for core-level nonvolatile power-gating
Daiki Kitagata, Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara (Tokyo Inst. of Tech.) ICD2017-10 Link to ES Tech. Rep. Archives: ICD2017-10
Abstract (in Japanese) (See Japanese page) 
(in English) Architectures and energy performance of nonvolatile SRAM (NV-SRAM) are demonstrated for nonvolatile power-gating (NVPG) that is a power-gating technique with nonvolatile state/data retention. The NV-SRAM cell consists of an ordinary 6T cell and two magnetic tunnel junctions (for nonvolatile retention) with two pass-transistors. The cell design and array architectures for leakage power reduction are developed. The SOTB CMOS technology is also introduced for the peripheral circuits to reduce the shut-down leakage. The break-even time (BET) that is an energy-performance index of NVPG is analytically formulated for arbitrary-array-size NV-SRAM with its peripheral circuits. The BET behavior with respect to the developed architectures are systematically analyzed by simulations and also using circuit parameters extracted from an implemented NV-SRAM TEG. A sufficiently short BET for the L1-cache-size NV-SRAM can be achieved, which would result in fine-grained core-level NVPG of multicore processors and SoCs.
Keyword (in Japanese) (See Japanese page) 
(in English) CMOS / standby power / power-gating / SRAM / nonolatile SRAM / microprocessor / SoC /  
Reference Info. IEICE Tech. Rep., vol. 117, no. 9, ICD2017-10, pp. 51-56, April 2017.
Paper # ICD2017-10 
Date of Issue 2017-04-13 (ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ICD2017-10 Link to ES Tech. Rep. Archives: ICD2017-10

Conference Information
Committee ICD  
Conference Date 2017-04-20 - 2017-04-21 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ICD 
Conference Code 2017-04-ICD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Architectures and energy performance of nonvolatile SRAM for core-level nonvolatile power-gating 
Sub Title (in English)  
Keyword(1) CMOS  
Keyword(2) standby power  
Keyword(3) power-gating  
Keyword(4) SRAM  
Keyword(5) nonolatile SRAM  
Keyword(6) microprocessor  
Keyword(7) SoC  
Keyword(8)  
1st Author's Name Daiki Kitagata  
1st Author's Affiliation Tokyo Institute of Technology (Tokyo Inst. of Tech.)
2nd Author's Name Yusuke Shuto  
2nd Author's Affiliation Tokyo Institute of Technology (Tokyo Inst. of Tech.)
3rd Author's Name Shuu'ichirou Yamamoto  
3rd Author's Affiliation Tokyo Institute of Technology (Tokyo Inst. of Tech.)
4th Author's Name Satoshi Sugahara  
4th Author's Affiliation Tokyo Institute of Technology (Tokyo Inst. of Tech.)
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Speaker Author-1 
Date Time 2017-04-21 09:35:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # ICD2017-10 
Volume (vol) vol.117 
Number (no) no.9 
Page pp.51-56 
#Pages
Date of Issue 2017-04-13 (ICD) 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan