講演抄録/キーワード |
講演名 |
2017-03-01 15:30
High accuracy 8*8 approximate multiplier based on OR operation ○Yi Guo・Heming Sun・Canran Jin・Shinji Kimura(Waseda Univ.) VLD2016-105 |
抄録 |
(和) |
(まだ登録されていません) |
(英) |
Approximate computing is a promising approach for error-tolerate applications. Multipliers contribute more area and delay in arithmetic circuits. In this paper, we develop a novel 8*8 approximate multiplier by (1) constructing from four 4*4 multiplication blocks and (2) utilizing OR operation on three lowest blocks for area reduction and accurate operation on one highest block to ensure high accuracy. Matlab simulation results illustrate that the approximate multiplier obtains the mean accuracy of 99.14%. Compared to the Wallace multiplier, our proposed multiplier implemented in a 90nm CMOS process reduces 32.32% and 17.17% in terms of area and delay, respectively. |
キーワード |
(和) |
/ / / / / / / |
(英) |
approximate computing / multiplier / high accuracy / / / / / |
文献情報 |
信学技報, vol. 116, no. 478, VLD2016-105, pp. 19-24, 2017年3月. |
資料番号 |
VLD2016-105 |
発行日 |
2017-02-22 (VLD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
著作権に ついて |
技術研究報告に掲載された論文の著作権は電子情報通信学会に帰属します.(許諾番号:10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
PDFダウンロード |
VLD2016-105 |