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| Presentation | 2017-02-21 12:00 An Approach to Performance Improvement of Machine Learning Based Fail Chip Discrimination Daichi Yuruki, Satoshi Ohtake (Oita Univ), Yoshiyuki Nakamura (Renesas System Design)  DC2016-77 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Today, advancements of semiconductor technology have progress to high integration of LSI circuits. A technique which keeps quality of LSIs and reduces test cost is necessary. In this work, we tackle this problem with machine learning techniques: learning test results of LSIs by machine learning from the test data of LSIs produced in the past, and prediction if a newly produced LSI is good or defective using intermediate test results of the LSI, i.e, the cost of remaining tests for the LSI can be reduced. In this paper, we propose several techniques for distinction precision of good products and defective products for the test cost reduction and evaluate them by performing experiments. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Data mining / clustering / discriminant analysis / LSI testing / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 116, no. 466, DC2016-77, pp. 17-22, Feb. 2017. | |
| Paper # | DC2016-77 | |
| Date of Issue | 2017-02-14 (DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | DC2016-77 |
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| Conference Information | |
| Committee | DC |
| Conference Date | 2017-02-21 - 2017-02-21 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | VLSI Design and Test, etc |
| Paper Information | |
| Registration To | DC |
| Conference Code | 2017-02-DC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Approach to Performance Improvement of Machine Learning Based Fail Chip Discrimination |
| Sub Title (in English) | |
| Keyword(1) | Data mining |
| Keyword(2) | clustering |
| Keyword(3) | discriminant analysis |
| Keyword(4) | LSI testing |
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| 1st Author's Name | Daichi Yuruki |
| 1st Author's Affiliation | Oita University (Oita Univ) |
| 2nd Author's Name | Satoshi Ohtake |
| 2nd Author's Affiliation | Oita University (Oita Univ) |
| 3rd Author's Name | Yoshiyuki Nakamura |
| 3rd Author's Affiliation | Renesas System Design Co., Ltd. (Renesas System Design) |
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| Speaker | Author-1 |
| Date Time | 2017-02-21 12:00:00 |
| Presentation Time | 25 minutes |
| Registration for | DC |
| Paper # | DC2016-77 |
| Volume (vol) | vol.116 |
| Number (no) | no.466 |
| Page | pp.17-22 |
| #Pages | 6 |
| Date of Issue | 2017-02-14 (DC) |
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