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| Presentation | 2016-11-28 14:15 Evaluation of Radiation-Hard Circuit Structures in a FDSOI Process by TCAD Simulations Kodai Yamada, Haruki Maruoka, Shigehiro Umehara, Jun Furuta, Kazutoshi Kobayashi (KIT)  VLD2016-49 DC2016-43 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | According to the Moore's law, LSIs are miniaturized and the reliability of LSIs is degraded. To improve the tolerance of FFs against soft errors, several redundant FFs are effective countermeasures. However, redundant FFs have large area, delay and power overheads. Non-redundant FF structures with higher soft-error resilience are needed. In this paper, we evaluate non-redundant FF structures in an FDSOI process to prevent soft errors. We evaluate soft error rates of latches with additional components such as capacitors or PMOS pass-transistors by TCAD simulations. Even by a particle hit with LET of 60 mev, the stored value of the latch with PMOS pass-transistors is not upset. Thus, the latch has enough tolerance to use even if in outer space. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Soft error / TCAD simulations / FDSOI / Radiation-hardened latch / Pass-transistor / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 116, no. 330, VLD2016-49, pp. 31-36, Nov. 2016. | |
| Paper # | VLD2016-49 | |
| Date of Issue | 2016-11-21 (VLD, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2016-49 DC2016-43 |
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| Conference Information | |
| Committee | VLD DC CPSY RECONF CPM ICD IE |
| Conference Date | 2016-11-28 - 2016-11-30 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Ritsumeikan University, Osaka Ibaraki Campus |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2016 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2016-11-VLD-DC-CPSY-RECONF-CPM-ICD-IE |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Evaluation of Radiation-Hard Circuit Structures in a FDSOI Process by TCAD Simulations |
| Sub Title (in English) | |
| Keyword(1) | Soft error |
| Keyword(2) | TCAD simulations |
| Keyword(3) | FDSOI |
| Keyword(4) | Radiation-hardened latch |
| Keyword(5) | Pass-transistor |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Kodai Yamada |
| 1st Author's Affiliation | Kyoto Institute of Technology (KIT) |
| 2nd Author's Name | Haruki Maruoka |
| 2nd Author's Affiliation | Kyoto Institute of Technology (KIT) |
| 3rd Author's Name | Shigehiro Umehara |
| 3rd Author's Affiliation | Kyoto Institute of Technology (KIT) |
| 4th Author's Name | Jun Furuta |
| 4th Author's Affiliation | Kyoto Institute of Technology (KIT) |
| 5th Author's Name | Kazutoshi Kobayashi |
| 5th Author's Affiliation | Kyoto Institute of Technology (KIT) |
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| Speaker | Author-1 |
| Date Time | 2016-11-28 14:15:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2016-49, DC2016-43 |
| Volume (vol) | vol.116 |
| Number (no) | no.330(VLD), no.331(DC) |
| Page | pp.31-36 |
| #Pages | 6 |
| Date of Issue | 2016-11-21 (VLD, DC) |
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