講演抄録/キーワード |
講演名 |
2016-03-04 14:45
A Design of 0.7-V 400-MHz All-Digital Phase-Locked Loop for Implantable Biomedical Devices ○Jungnam Bae・Saichandrateja Radhapuram・Ikkyun Jo・Weimin Wang(Osaka Univ.)・Takao Kihara(Osaka Institute of Tech.)・Toshimasa Matsuoka(Osaka Univ.) MW2015-212 ICD2015-135 エレソ技報アーカイブへのリンク:MW2015-212 ICD2015-135 |
抄録 |
(和) |
(まだ登録されていません) |
(英) |
A low-voltage controller-based all-digital phase-locked loop (ADPLL) uti
lized in the medical implant communication service (MICS) frequency band
was designed in this study. In the proposed design, controller-based lo
op topology is used to control the phase and frequency to ensure the rel
iable handling of the ADPLL output signal. A digitally-controlled oscill
ator with a delta-sigma modulator was employed to achieve high frequency
resolution. The phase error was reduced by a phase selector with a 64-p
hase signal from the phase interpolator. Fabricated using a 130-nm CMOS
process, the ADPLL consumes 840 μW from a 0.7-V supply voltage, and has
a settling time of 80 μs. The phase noise was measured to be -114 dBc/
Hz at an offset frequency of 200 kHz. |
キーワード |
(和) |
/ / / / / / / |
(英) |
All-Digital Phase-Locked Loop / Controller / Digitally-Controlled Oscillator / Phase Interpolator / MICS / / / |
文献情報 |
信学技報, vol. 115, no. 477, ICD2015-135, pp. 217-222, 2016年3月. |
資料番号 |
ICD2015-135 |
発行日 |
2016-02-24 (MW, ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
著作権に ついて |
技術研究報告に掲載された論文の著作権は電子情報通信学会に帰属します.(許諾番号:10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
PDFダウンロード |
MW2015-212 ICD2015-135 エレソ技報アーカイブへのリンク:MW2015-212 ICD2015-135 |