| IEICE Technical Committee Submission System Conference Paper's Information |
Online Proceedings [Sign in] Tech. Rep. Archives |
| Go Top Page | Go Previous | [Japanese] / [English] |
| Paper Abstract and Keywords | ||
| Presentation | 2015-12-03 10:50 On Correction of Temperature Influence to Delay Measurement in FPGAs Takeru Kina, Yousuke Miyake, Yasuo Sato, Seiji Kajihara (KIT)  VLD2015-63 DC2015-59 |
|
| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | As a means for delay testing for VLSIs in field, a measurement method of a path delay for a logic circuit using variable test timing has been proposed. However, the measured delay in the field is varied by temperature at test, because the temperature affects the circuit delay in the chip. Correction of influence by temperature variation upon the delay is required in order to compare the measured delay at different times. In this paper, the influence of the temperature during testing on the measured delay value is evaluated using a delay measurement circuit in an FPGA. Then, this paper proposes a correction technique of temperature influence on the measured delay using on-chip delay measurement, in order to realize delay measurement which does not depend on the temperature during testing in the field. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | FPGA / Logic BIST / Delay measurement / Variable test timing / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 115, no. 339, DC2015-59, pp. 165-170, Dec. 2015. | |
| Paper # | DC2015-59 | |
| Date of Issue | 2015-11-24 (VLD, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2015-63 DC2015-59 |
|
| Conference Information | |
| Committee | VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
| Conference Date | 2015-12-01 - 2015-12-03 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Nagasaki Kinro Fukushi Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2015 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | DC |
| Conference Code | 2015-12-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | On Correction of Temperature Influence to Delay Measurement in FPGAs |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | Logic BIST |
| Keyword(3) | Delay measurement |
| Keyword(4) | Variable test timing |
| Keyword(5) | |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Takeru Kina |
| 1st Author's Affiliation | Kyushu Institute of Technology (KIT) |
| 2nd Author's Name | Yousuke Miyake |
| 2nd Author's Affiliation | Kyushu Institute of Technology (KIT) |
| 3rd Author's Name | Yasuo Sato |
| 3rd Author's Affiliation | Kyushu Institute of Technology (KIT) |
| 4th Author's Name | Seiji Kajihara |
| 4th Author's Affiliation | Kyushu Institute of Technology (KIT) |
| 5th Author's Name | |
| 5th Author's Affiliation | () |
| 6th Author's Name | |
| 6th Author's Affiliation | () |
| 7th Author's Name | |
| 7th Author's Affiliation | () |
| 8th Author's Name | |
| 8th Author's Affiliation | () |
| 9th Author's Name | |
| 9th Author's Affiliation | () |
| 10th Author's Name | |
| 10th Author's Affiliation | () |
| 11th Author's Name | |
| 11th Author's Affiliation | () |
| 12th Author's Name | |
| 12th Author's Affiliation | () |
| 13th Author's Name | |
| 13th Author's Affiliation | () |
| 14th Author's Name | |
| 14th Author's Affiliation | () |
| 15th Author's Name | |
| 15th Author's Affiliation | () |
| 16th Author's Name | |
| 16th Author's Affiliation | () |
| 17th Author's Name | |
| 17th Author's Affiliation | () |
| 18th Author's Name | |
| 18th Author's Affiliation | () |
| Speaker | Author-1 |
| Date Time | 2015-12-03 10:50:00 |
| Presentation Time | 25 minutes |
| Registration for | DC |
| Paper # | VLD2015-63, DC2015-59 |
| Volume (vol) | vol.115 |
| Number (no) | no.338(VLD), no.339(DC) |
| Page | pp.165-170 |
| #Pages | 6 |
| Date of Issue | 2015-11-24 (VLD, DC) |
[Return to Top Page]