Paper Abstract and Keywords |
Presentation |
2015-12-03 10:50
[Invited Talk]
Development of Via Structures in IC Package Substrates for Impedance Reduction Tomoyuki Akaboshi, Taiga Fukumori, Daisuke Mizutani, Motoaki Tani (Fujitsu Lab.) CPM2015-136 ICD2015-61 Link to ES Tech. Rep. Archives: CPM2015-136 ICD2015-61 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
This paper describes the impedance reduction technologies in build-up package substrates for high performance CPU, such as enterprise servers or super computers. The layer connection structures of the power supply path were improved by changing a via formation in build-up substrate. As a result, we have found a via structure that improves the electrical characteristics while also yielding good connectivity and productivity. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Build-up substrate / Via structure / Impedance / Power Integrity / Reliability test / / / |
Reference Info. |
IEICE Tech. Rep., vol. 115, no. 340, CPM2015-136, pp. 51-54, Dec. 2015. |
Paper # |
CPM2015-136 |
Date of Issue |
2015-11-24 (CPM, ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
CPM2015-136 ICD2015-61 Link to ES Tech. Rep. Archives: CPM2015-136 ICD2015-61 |
Conference Information |
Committee |
VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
Conference Date |
2015-12-01 - 2015-12-03 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Nagasaki Kinro Fukushi Kaikan |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2015 -New Field of VLSI Design- |
Paper Information |
Registration To |
CPM |
Conference Code |
2015-12-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Development of Via Structures in IC Package Substrates for Impedance Reduction |
Sub Title (in English) |
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Keyword(1) |
Build-up substrate |
Keyword(2) |
Via structure |
Keyword(3) |
Impedance |
Keyword(4) |
Power Integrity |
Keyword(5) |
Reliability test |
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1st Author's Name |
Tomoyuki Akaboshi |
1st Author's Affiliation |
FUJITSU LABORATORIES LTD. (Fujitsu Lab.) |
2nd Author's Name |
Taiga Fukumori |
2nd Author's Affiliation |
FUJITSU LABORATORIES LTD. (Fujitsu Lab.) |
3rd Author's Name |
Daisuke Mizutani |
3rd Author's Affiliation |
FUJITSU LABORATORIES LTD. (Fujitsu Lab.) |
4th Author's Name |
Motoaki Tani |
4th Author's Affiliation |
FUJITSU LABORATORIES LTD. (Fujitsu Lab.) |
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Speaker |
Author-1 |
Date Time |
2015-12-03 10:50:00 |
Presentation Time |
50 minutes |
Registration for |
CPM |
Paper # |
CPM2015-136, ICD2015-61 |
Volume (vol) |
vol.115 |
Number (no) |
no.340(CPM), no.341(ICD) |
Page |
pp.51-54 |
#Pages |
4 |
Date of Issue |
2015-11-24 (CPM, ICD) |
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