Paper Abstract and Keywords |
Presentation |
2015-12-02 16:20
Formulation to SAT for Acceleration in 1D Layout Area Minimization of CMOS circuits Hayato Mashiko, Yukihide Kohira (Univ. of Aizu) VLD2015-51 DC2015-47 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In layout design for LSI circuits, the layout area is minimized to reduce the fabrication cost and to increase the yield of LSI chips. In this thesis, we focus on a 1D layout design of CMOS circuits, where the height can be fixed. In the 1D layout of CMOS circuits, the width minimization corresponds to the maximization of the number of shared diffusions and the height minimization corresponds to the minimization of the number of tracks. The 1D layout area minimization method using SAT solver has been proposed for CMOS circuits so that the number of shared diffusions is maximized with the minimum number of tracks. However, since the formulations of the constraints and the objective function to SAT are ineffective in the existing method, its computational time is long. In this research, we propose new formulations of constraints and an objective function to SAT for acceleration. To confirm the effectiveness of the proposed method, the experimental results between the existing method and the proposed method are compared. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
CMOS circuit / 1D layout / layout area minimization / SAT / acceleration / / / |
Reference Info. |
IEICE Tech. Rep., vol. 115, no. 338, VLD2015-51, pp. 81-86, Dec. 2015. |
Paper # |
VLD2015-51 |
Date of Issue |
2015-11-24 (VLD, DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2015-51 DC2015-47 |
Conference Information |
Committee |
VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
Conference Date |
2015-12-01 - 2015-12-03 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Nagasaki Kinro Fukushi Kaikan |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2015 -New Field of VLSI Design- |
Paper Information |
Registration To |
VLD |
Conference Code |
2015-12-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Formulation to SAT for Acceleration in 1D Layout Area Minimization of CMOS circuits |
Sub Title (in English) |
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CMOS circuit |
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1D layout |
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layout area minimization |
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SAT |
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acceleration |
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1st Author's Name |
Hayato Mashiko |
1st Author's Affiliation |
The University of Aizu (Univ. of Aizu) |
2nd Author's Name |
Yukihide Kohira |
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The University of Aizu (Univ. of Aizu) |
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Speaker |
Author-1 |
Date Time |
2015-12-02 16:20:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2015-51, DC2015-47 |
Volume (vol) |
vol.115 |
Number (no) |
no.338(VLD), no.339(DC) |
Page |
pp.81-86 |
#Pages |
6 |
Date of Issue |
2015-11-24 (VLD, DC) |
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